Autumn-Spring 2024-2025

This release contains binaries for Windows (x64), macOS (x64 and arm64), and Linux (x64) for production use for the Autumn and Spring terms of 2024-2025. Find the correct correct binary or disk image for your operating system as below:

• Windows (x64): issie-5.2.2-win-x64.zip (How to install and run the binaries on your machine);
• macOS (arm64, or Apple Silicon Macs): issie-5.2.2-macos-arm64.dmg;
• macOS (x64, or Intel Macs): issie-5.2.2-macos-x64.dmg;
• Linux (x64): issie-5.2.2-linux-x64.zip, unzip the file, and run Issie like: /path/to/issie/binary --no-sandbox (v5.2.2 compilation pending).

The main changes from last year are fixing some quite bad but never reported memory leaks, and large improvements to the waveforms simulator. This has been a challenging part of Issie to get right but it is now very usable, even on long simulations. In addition the code has had major refactoring to make future development & maintenance.

• Credit for the initial waveform simulator scrollbar and on-demand waveform generation goes to Samuel Wang.
• Credit for the memory leak fixes goes to Tom Clarke.
• Credit for bringing the memory leak to the attention of the developers goes to Radaan Madhan.
• Please could any bugs found in this v5.2.x release be reported ASAP! They can be fixed.

v5.2.2

• Fixed: vertical scrollbar for large truth tables.
• Thanks to LH-AND-FPGA for the fix

v5.2.1

• feat: waveform simulator start/view error UI made consistent with step simulation UI
• fixed: small bugs in waveform simulator top-level UI

v5.2.0

Fixed from last year

• Fix: a bad memory leak #463 that caused slowdown and crashes when working on medium-sized or bigger designs
• Fix: a different memory leak that caused crashes when repeating very long waveform simulations of large designs
• Fix: many minor issues
• Fix (internal) waveform simulator has been refactored as 8 separate source files and is now easy to work on.

New Features

• Waveform Simulation improvements
  • Feat: a (very nice) responsive software horizontal scrollbar. Waveforms are now generated on demand only for the visible clock cycles.
  • Feat: waveform numeric values positioned better for legibility
  • Feat: waveforms grey out nicely when numeric values are too long to print.
  • Feat: numeric values have been shortened: the 0 in front of radixed numbers is omitted, and the radix itself is omitted when the numbers are single digit.
  • Feat: waveforms scroll vertically if necessary separately from simulator top controls and the RAM viewer.
  • Feat: usable simulating up to 1,000,000 clock cycles
  • Feat: a new RAM viewer windowed mode for viewing RAMs that have a large number of non-zero memory locations
  • Feat: a super-zoom feature for viewing long waveforms
  • Feat: configuration popup for changing font sizes and other parameters
  • Feat: rationalised top controls with new help buttons
  • Feat: arrow keys control highlighted cycle
• Feat: arbitrary length busses - previous limitations on constants, bus compare, memory have been removed so all of Issie will work with up to 16384 bit busses.
• Feat: very long bus-width number printing has been improved
• Feat: new Eratosthenes Sieve demo shows waveforms over 800,000 cycles and all of RAM written.

Summer Release with new waveform viewer & 2023-4 memory leak fixed

This release incorporates a new design for the waveform simulator with a software scrollbar and greatly improved performance. It also fixes a major problem working on big designs affecting v4 and v3 - a memory leak leading to slow operation and then crashing.

v5.1.20

• Feat: add button to RAM link menu
• Fix: stop save button spurious highlighting

v5.1.18

• Feat: Add left/right arrows for waveform simulator navigation

v5.1.17

• Feat: use button spinner not progress bar for all waveform generation

v5.1.16

• Major refactor of new top-level simulation
• Fix: focus
• Fix: unnecessary simulation

v5.1.15

• Feat: new-style simulation triggers (should be more robust)
• Fix: simulation continuity problems

v5.1.14

• Fix: make RAM display work properly with sampling zoom.
• Fix: adjust clock cycle limits

v5.1.13

• Fix: add error boundaries to waveform & RAM simulation views

v5.1.12

• Feat: consistent loading spinner and progress bar during big simulation waits
• Fix: hovered label appearance
• Fix: values column width
• Feat: better waveform RAM display

v5.1.11

• Fix: Error in super-zoom sampling
• Fix: Lock / unlock is now saved and locked sheets cannot be read
• Feat: Update demos
• Fix: memory contents not updated when step simulation is started
• Feat: refactoring & rationalisation of simulation code

v5.1.10

• Fix RAM viewer for full RAMs
• Further tuning for long simulations

v5.1.9

• feat: printing very long numbers nicely compressed, partial implementation - still not quite right
• fix: new fastsim overwritten causing crashes

v5.1.8

• Fix: extra digit in hex and binary displays (regression from 5.0.0)
• Fix: memory leak from discarded FastSimulations (noticed when these are large)
• Feature: config warning uses array size estimate

v5.1.7

• Fix: cursor missing regression in 5.1.6

v5.1.6

• Fix: widths of text in waveform simulator for different font sizes

v5.1.5

• Feature: user-friendly waveform simulator configuration popup
• Feature: space-minimise number printing

v5.1.4

• Polish Waveform Simulator
• Fix: many obscure navigation-related bugs
• Fix: scroll mouse-up not always recognised
• Improve instructions

v5.1.3

• Feature: "sample-based" zoom
• Much polishing of waveform simulator
• Fix a number of rare but bad bugs in waveform simulator
• Feature: hide extra zoom when not needed

v5.1.2

• Polish dimensions, add needed scrollbars
• Highlight current sheet on breadcrumbs

v5.1.1

• Alpha release of new waveform simulator UI with better scrolling

v5.1.0

• Small polishing from v5.0.9.
• Memory leakage now declared fixed!
• Some garbage collector (gc) tuning
• Large increases in speed and usability when working on big designs
• Run from terminal (windows .\issie.exe) to view gc statistics

v5.0.9

• More memory debug features
• One major memory leak fixed
• Not clear whether there remains any leak

v5.0.6

• Alpha release - with debug feature added
• Changes to minimise and investigate memory leak bug

v5.0.0

• Feature: New scrollbar
• Feature: Make waveform SVGs trimmed to the correct size on demand
• Feature: better waveform display for numeric waveforms
• Fix: #447
• Fix: #442
• Fix: #448

Bugfix alpha release

This release has some experimental changes that may prevent - or minimise - the Issie memory leak that causes slowdown and then crash when Issie is used for a long time with large designs.

It is an ALPHA release - the changes made may have introduced a few UI bugs.

Autumn & Spring Term Release

Issie with Summer additions as used in Autumn & Spring Term 2023

• Thanks to FYP students Yujie Wang (speed up Simulator) and Petra Ratkai (Verilog compiler)
• Thanks to the Summer UROP students:
  • Samuel Tan
  • Theo Gkamaletsos
  • Lu Ju
• Thanks to the unpaid but very productive Summer Issie Developer Community students
  • Luke Hedley
  • Lucas Ng
  • Constantin Kronbichler
  • Ilan Iwumbwe
• Thanks to HLP class of 2023 for the better auto-routing, rotate and scale, and other enhancements scheduled for next year
• Thanks to Tom Clarke for the new Wire auto-Separation module

v4.1.3

• Fix: demo projects cannot be loaded under macos
• Fix: current sheet is not saved when importing a sheet
• Fix: new IssieStick ID

v4.1.2

This fixes a number of minor bugs (everything found in Autumn term or before that). No new functionality for Spring; curly-style gates + better waveform selection will be delayed now till Summer. Sorry!

• fix bug that prevented import sheet on macos
• fix bug that crashes Issie if SplitN or MergeN size is reduced
• increase previously very low limit on gate inputs
• improve catalog hints & UI, and Properties UI, for SplitN, MergeN, Gates

v4.1.1

• Fix bug on macos only that greys out all sheets when using Import Sheet

v4.1.0

• Initial release includes all additions except new breadcrumb-based waveform selector (scheduled for v4.1.1 if it can be done in time).
• Curvy-style gates in the end did not get added. Doing them nicely with N-input gates was too much work, but is on roadmap.
• Very many additions from last year:
  • Improved UI for step simulation with back and forwards
  • Improved UI for top-level waveform simulation (consistent step simulation)
  • Improved auto-routing of wires with auto-separation - very little manual adjustment now needed
  • Add sheet to project function
  • Breadcrumbs for sheet selector that display design hierarch visually
  • Right-click context menus throughout draw block
  • Direct right-click navigation from custom components to sheets with "Back" button to return.
  • Simulation 17X faster than last year
  • New NC component and auto-hints to use it to close unused outputs.
  • Hint pane to highlight otherwise obscure features.
  • Custom component scaling via drag
  • Rotate and scale for multiple selected components
  • New components: mergeN and splitN
  • New components: logic gates can now have N inputs. Currently N <=4 for no good reasons. Will allow N <=16 v4.1.1.
  • Built-in demo designs
  • Improved Verilog compiler (not scheduled for production use yet)
  • Too many bug fixes to mention

Summer 2023 "Add features" release

This is the alpha release of Issie with improvements from 2023 work. It is slightly less stable than Issie normally, but mainly is alpha because it is expected that new features from 2023 work will continue to be added over the Summer.

Binaries will be updated on this release, with new tags, till Issie is ready for the Autumn Term v4.1.0 production release. (NB binaries will be labelled 4.0.1 etc because 4.0.a.1 is not allowed - however Issie versions will be correct).

v4.0.a.14

1. Many UI improvements and bug fixes throughout
2. Web workers added and tested - but not yet used.
3. Built-in demo designs added

v4.0.a.13

1. fix Ctrl-W so it always works changing sheets
2. Misc UI improvements, tooltips, responsiveness.
3. Reduce unnecessary saving of sheets.

v4.0.a.12

1. Various fixes to multi-symbol rotate and scale
2. fix obscure bug in separation code
3. reduce separation so circuits do not need saving immediately after load

v4.0.a.11

1. Replace sheets menu by new breadcrumbs hierarchy with right-click ops.

v4.0.a.10

1. Added 3 & 4 input gates
2. Added "add sheet" function (NB some improvement is still expected for complex cases)
3. Added right-click context menus to draw block objects

Fixes:

• Custom symbol size change

v4.0.a.9

1. Increase default wire separation
2. Fix bug when dragging segments

v4.0.a.8

1. improve separation: do not separate close same-net segments
2. When dragging multiple segments, all segments move together

v4.0.a.7

1. Fix top-level rerouting command

v4.0.a.6

1. Various improvements to separation - it should now be almost perfect
2. Edit menu commands to invoke reseparation, or autoroute and separation.

v4.0.a.5

1. Fix squiggly wire artifacts in new-style wire routing and separation
2. Fix N-bit NOT display bug
3. Add hint to custom component port movement and scaling ops
4. Various small fixes

v4.0.a.4

1. Fix a serious bug preventing IOLabel from simulating which was introduced by 338f4b1

v4.0.a.3 --- Contains IOLabel simulation bug - don't use

1. Add "not connected" component
2. Mend simulator bug regression introduced by fdd56a7

v4.0.a.2 --- Contains IOLabel simulation bug - don't use

1. Lots of internal changes
2. Make truth tables work
3. Verilog compiler + components added

v4.0.a.1

1. Add new (better) wire routing.
2. Add wire separation
3. Add multi-symbol scale and rotate

Autumn/Spring 2022

This is the production release for DECA 2022/23. There have been a lot of UI changes and additions since last year. So even though it is not tagged beta we expect a few issues, but hope for nothing major.

Please post issues if you discover any problems, or things you wish were better!

Current: v3.0.11 - see below for changes

Version Change Notes

v3.0.11

• Bug Fix - simulation not advanced exception in waveform simulator when viewing ram
• Bug Fix - < 32 bit counter component in some circumstances creates a simulation exception
• Bug Fix - incorrect step simulator results for > 1000 steps

v3.0.10

• Bug Fix #268 - changing the name of wire labels now correctly changes circuit error status
• Feature. Radix selector is now displayed in step simulation with multi-bit viewers. (This was not true if there were no other multi-bit displays)
• Improve split/merge component descriptions so they highlight vertical flipping to put MSB at top.

v3.0.9

• Feature: allow _ in component and sheet names

v3.0.8

• Fix bug which crashes waveform viewer in some cases

v3.0.7

• Fix transient bug which causes waveforms to be blank
• Improve waveform viewer help text

v3.0.6

• Fix negative numbers display in sDec radix inside wave simulator
• Make value column width adjustable in wave simulator

v3.0.5

• Fix > 32 bit busses
• Improve waveform simulation display

v3.0.4

Features:

• Selected Truth tables can now be selected from selected components without also needing all internal connections
• Truth-table columns can be moved left or right (See #254)

v3.0.3

Bug fixes:

• fix #256
• fix #257

v3.0.2

Minor changes:

• Improve custom component auto-sizing based on ports positions and names
• Improve theme colors (small changes)
• Improve properties dialog focus

v3.0.2.beta1

• fix #249 (still published as v3.0.1)

v3.0.1

• Pull together all of the Summer work
• Final changes from v3.0.0
  • Make bus compare constant definitions multi-radix consistent with constant definitions
  • Add shifts by numbers on busses to Verilog language accepted for Verilog components
  • Close some minor bugs from issues

Major changes from 2021/2022 - initial release notes

The code is now 36K lines (from 20K last year).

• Better Schematic Editor - components can be rotated/flipped. Auto-routing works better and from any edge of a component. Manual routing combines with auto-routing smoothly. Smart snapping makes it easier to position components
• Better Custom Components. The symbols instantiating subsheets can now have ports moved to any side of component with drag-and-drop UI. Components can have size scaled.
• Sheets descriptions can now be added, This appears in Sheet properties window and info boxes on sheet menu for rapid exploration of designs
• New components and additional properties on old components, fill in gaps.
  • Counter (optional enable, load).
  • N bit Adder (optional Cin, Cout)
  • N bit Not gate, AND, OR.
  • 2, 4, 8 input MUX and 2,4,8 output DEMUX to match. 2-input MUX has inputs switchable in position relative to select.
  • Bus spreader (1 bit -> N bits)
• Verilog design entry. New editor window with great error messages allows combinational logic to be implemented as Verilog equations
• New Waveform Viewer
  • One thing contentious - no scroll bar!
  • Can select any waveform on any sheet while simulating
  • Designs can be edited (any sheet) while running simulation, and simulation refreshed with a single click to see changes
  • UI is now consistent with Step simulator
  • Non-zero values on inputs allowed: default values are used and these can be set from Input properties or from step simulator
  • Components and connections highlight hovering over wave names (if the sheet the wave is on is selected
  • New hierarchical waveform selector (we think it is better, an it scales to very large designs)
  • Progressive simulation means simulation time is less noticeable
  • Progress bars for long waits in simulation or waveform generation (if 100s of waveforms are selected slowing this down) make a better UI
• Update memory linking to files. Memories now have a decent UI for linking initial contents to files. File change auto-updates a design - and then single click in waveform simulator will show results of simulating with new data. Should help work in Spring
• Truth table generator
  • Can show whole sheet or any selected part
  • Provides binary truth tables, with don't cares to simplify
  • Provides algebraic truth tables with good simplification of algebraic expressions
• Minor negative - as result of algebraic evaluation the simulator is now about 30% slower than last year. A simulation overhaul with a much faster reimplementation is scheduled for 2023
• Issie Stick supported. A one-click UI interfaces to external open source synthesis software to put designs onto a purpose-built EEE FPGA board so they drive real hardware. This is still experimental but the basic functionality now works.

Pretty well all the feature requests from last year have been implemented as well as a lot of things that make the UI more consistent and ergonomic.

July/August Integration

Integrate summer FYP work into Issie.

3.0.0beta.10

• new color themes
• new simulation and waveform generation with progress bars on waits > 300ms (adjustable)
• some bug fixing
• new components polished
• memories linked to files auto-update
• Issie stick integration

3.0.0beta.9

• Integrate new components: counter, bit spreader
• Make CIN, COUT ports on adder optional
• Make switching MUX2 inputs possible
• Change background
• Add descriptions to sheets
• Optionally scale height and width of custom components
• Improve wavesim geometry

3.0.0beta.8

• Highlight all connections, and all labels on wave name hover
• Push input defaults from input state in step simulator, add defaults to step simulator
• Small polishing to waveform simulator

3.0.0beta.7

• Mend waveform simulator bug preventing editing while running simulator
• Improve info boxes
• Add default values to inputs

3.0.0beta.6

• Remake waveform simulator UI consistent with step simulator
• Major refactoring to allow waveform selection and simulation across all design sheets (it is about optimal)
• Technical debt reduction (painful) around how simulator is used
• Fix waveform simulator HTML/CSS
• Many fixes and improvements to verilog components

3.0.0beta.5

• integrate new waveform simulator

Post-Spring Term Releases

This is a beta version with the new draw block implemented by 2022 HLP class, which allows auto-routing with symbols rotated and flipped. A number of other enhancements have been folded in.

Main New Features

• All components can be rotated and flipped.
• Custom component ports can be reordered, and moved to different sides by dragging (Ctrl/drag).
• Custom components auto-resize.
• Clock symbols are shown on custom components that contain clocked logic.
• Wires can be styled with jumps (old Issie), modern wires (no jumps, black circles indicate connection), or radiused (prettier).
• Wires have optional arrows to disambiguate direction.
• Component labels can be repositioned by dragging, or rotating.
• Wires snap to same net wires on dragging, making it easy to position neatly.
• Components snap to alignment with other components, and to wires having no kinks, on dragging.
• Components can be aligned or distributed.
• Components are resized for better usability and slimline versions of Bus Select and Wire Label are now used.
• Persistent data is now available so that last project and wire style is remembered.
• Fit-to-window is now improved (circuits are centred on sheet) and done automatically on loading a sheet.

Details

3.0.0beta.4

• Add recent files to project menu. Closes #9

3.0.0beta.3

• Bug fix

  • fix label changes when copying component with properties open bug #144

• Feature

  • Add popup from edit meu item documenting port movement

3.0.0beta.2

• Bug fixes
  • fix wire update when symbols move after arrangement
  • fix rare bug on load only of large circuits where cursor is misaligned with sheet

3.0.0beta.1

• Add symbol arrangement
  • Selected symbols can be aligned, or distributed, vertically or horizontally
  • Orientation is determined automatically based on symbol poistions
  • Symbols labels can be rotated (independently of symbols)

3.0.0beta.0

• Patch so that very old (last year's) designs can be loaded correctly
• Persist directory and wire style options in browser local data
• Improve fitToWindow, run it automatically on sheet load
• Improve legacy wire import, segment combine, and segment split to make draggable
• Improve component legends
• Improve component sizing
• Make label movement more responsive
• After wire segment drag, automatically combine segments where this is possible after snap together.
• Improve label highlighting
• Mend bug in label position on pasting
• Allow rotation/flip of custom components
• Make label color change when component is selected
• Prevent unnecessary popups when changing port vertical order on design sheets
• Match symbols better for alignment snaps
• Make snapping more consistent
• Polish UI, menus, view
• Make snap work better
• Mend bug in snap logic that caused occasional glitches when moving components
• Increase precision of wire selection so that the nearest segment to cursor crosshairs is always dragged
• Prevent numeric labels from being input
• Better bus select (now with empty label as allowed default)
• Make empty labels unclickable
• Better mend of label positioning
• Better font for labels
• Better wire label symbols
• Make default positioning of added ports on custom components correct
• Mend label positioning
• Mend crash on custom component port change from another sheet

New Schematic Editor Alpha releases

• Update binaries 16/4/22
  • Patch so that very old (last year's) designs can be loaded correctly
  • Persist directory and wire style options in browser local data
• Update binaries 15/4/22 21:45
  • Improve fitToWindow
  • Run it automatically on sheet load
• Update binaries 15/4/22
  • Improve legacy wire import, segment combine, and segment split to make draggable
  • Improve component legends
  • improve component sizing
• Update binaries 12/4/22 23:00
  • Make label movement more responsive
  • After wire segment drag, automatically combine segments where this is possible after snap together.
• Update binaries 11/4/22 23:00
  • Improve label highlighting
• Update binaries 11/4/22
  • Mend bug in label position on pasting
• Update binaries 10/4/22 22:47
  • Allow rotation/flip of custom components
  • Make label color change when component is selected
  • Prevent unnecessary popups when changing port vertical order on design sheets
  • Match symbols better for alignment snaps
• Update binaries 10/4/22
  • Make snapping more consistent
  • Polish UI, menus, view
• Update binaries 9/4/22
  • Make snap work better
  • Mend bug in snap logic that caused occasional glitches when moving components
• Update binaries 7/4/22 23:35
  • Increase precision of wire selection so that the nearest segment to cursor crosshairs is always dragged
• Update binaries 7/4/22 20:40
  • Prevent numeric labels from being input
  • Better bus select (now with empty label as allowed default)
  • Make empty labels unclickable
• Update binaries 7/4/22 00:05 -
  • Better mend of label positioning
  • Better font for labels
  • Better wire label symbols
  • Make default positioning of added ports on custom components correct
• Update binaries 5/4/22 14:55 -
  • mend label positioning
  • mend crash on custom component port change from another sheet

This is an experimental release of the new greatly enhanced Schematic Editor with improvements written by 3rd year students doing HLP. It will have bugs.

Main features:

• components can be rotated and flipped
• custom component ports can be reordered, and moved to different sides
• clock symbols on custom components that need clocks
• Prettier wires (3 different versions).
• component labels can be graphically moved
• some bugs that required rewrite now fixed
• NB - many issues will be closed by these features, however issues are left open till we have finished the additions

Various other improvements and fixes are expected over Easter. If your favourite request is not yet done add a comment to the issue!

Spring Term Minor Bug Fixes

2.4.5

• Fix rare bug where app can become unresponsive after detecting a simulation error

v2.4.4

• Fix unpleasant feature where component instances auto-updated would not automatically save, forcing repeat auto-update dialogs.
• Closes #130 .

v2.4.3

• Fix bug (feature) where ctrl keys used on popup propagate to underlying diagram
• Closes #126

v2.4.2

• Fix a very rare bug where manual copying of design files - so there are two differently names files with same contents - can cause ISSIE to crash. Upgrade from 2.4.1 only needed if Issie crashes (white screen) on loading a sheet on your design.

v2.4.1

• Fix bug where trying to view an async ROM in waveform simulator causes a crash
• arm64.dmg binary now generated from an M1 mac. Could somone with an M1 Mac please try it and see if it will work? It works on the dev machine - but macs sometimes have weird signing issues. If works it should be a good speedup from running the old Intel dmg under Rosetta 2 (which you can do anyway).