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@tomcl tomcl released this 27 Sep 12:18
· 178 commits to master since this release
v4.1.3
8d6e72d

Issie with Summer additions as used in Autumn & Spring Term 2023

  • Thanks to FYP students Yujie Wang (speed up Simulator) and Petra Ratkai (Verilog compiler)
  • Thanks to the Summer UROP students:
    • Samuel Tan
    • Theo Gkamaletsos
    • Lu Ju
  • Thanks to the unpaid but very productive Summer Issie Developer Community students
    • Luke Hedley
    • Lucas Ng
    • Constantin Kronbichler
    • Ilan Iwumbwe
  • Thanks to HLP class of 2023 for the better auto-routing, rotate and scale, and other enhancements scheduled for next year
  • Thanks to Tom Clarke for the new Wire auto-Separation module

v4.1.3

  • Fix: demo projects cannot be loaded under macos
  • Fix: current sheet is not saved when importing a sheet
  • Fix: new IssieStick ID

v4.1.2

This fixes a number of minor bugs (everything found in Autumn term or before that). No new functionality for Spring; curly-style gates + better waveform selection will be delayed now till Summer. Sorry!

  • fix bug that prevented import sheet on macos
  • fix bug that crashes Issie if SplitN or MergeN size is reduced
  • increase previously very low limit on gate inputs
  • improve catalog hints & UI, and Properties UI, for SplitN, MergeN, Gates

v4.1.1

  • Fix bug on macos only that greys out all sheets when using Import Sheet

v4.1.0

  • Initial release includes all additions except new breadcrumb-based waveform selector (scheduled for v4.1.1 if it can be done in time).
  • Curvy-style gates in the end did not get added. Doing them nicely with N-input gates was too much work, but is on roadmap.
  • Very many additions from last year:
    • Improved UI for step simulation with back and forwards
    • Improved UI for top-level waveform simulation (consistent step simulation)
    • Improved auto-routing of wires with auto-separation - very little manual adjustment now needed
    • Add sheet to project function
    • Breadcrumbs for sheet selector that display design hierarch visually
    • Right-click context menus throughout draw block
    • Direct right-click navigation from custom components to sheets with "Back" button to return.
    • Simulation 17X faster than last year
    • New NC component and auto-hints to use it to close unused outputs.
    • Hint pane to highlight otherwise obscure features.
    • Custom component scaling via drag
    • Rotate and scale for multiple selected components
    • New components: mergeN and splitN
    • New components: logic gates can now have N inputs. Currently N <=4 for no good reasons. Will allow N <=16 v4.1.1.
    • Built-in demo designs
    • Improved Verilog compiler (not scheduled for production use yet)
    • Too many bug fixes to mention
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