⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷
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Updated
Mar 26, 2024 - HTML
⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
x mega menu is repsonsive mega menu based on vannilajs
Responsive vertical navigation menu
30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
Gatery, a library for circuit design.
The Repository contains the code of various Digital Circuits
📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip
RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24
Template project for using gatery
RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor
Design of a BIST module for RISC-V fault testing
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
Digital Logical Designs Course Projects
BDD Gherkin implementation in native SystemVerilog, based on UVM.
This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and SystemC-AMS libraries. Spring 2022
probable journey of RTL coding ft. Chandra Prakash
Verification of D-FF using UVM on EDA playground
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