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[SelectionDAG] Allow FREEZE to be hoisted before integer SETCC.
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Add integer ISD::SETCC to canCreateUndefOrPoison.
Add ISD::CONDCODE to isGuaranteedNotToBeUndefOrPoison.

Recovers some regression from llvm#84232.
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@topperc
topperc committed Mar 6, 2024
1 parent 3b50859 commit fc2a390
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Showing 7 changed files with 99 additions and 114 deletions.
6 changes: 6 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4998,6 +4998,7 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op,
return true;

switch (Opcode) {
case ISD::CONDCODE:
case ISD::VALUETYPE:
case ISD::FrameIndex:
case ISD::TargetFrameIndex:
Expand Down Expand Up @@ -5090,6 +5091,11 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
case ISD::BUILD_PAIR:
return false;

case ISD::SETCC:
// Integer setcc cannot create undef or poison.
// FIXME: Support FP.
return !Op.getOperand(0).getValueType().isInteger();

// Matches hasPoisonGeneratingFlags().
case ISD::ZERO_EXTEND:
return ConsiderFlags && Op->getFlags().hasNonNeg();
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/RISCV/alu64.ll
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Expand Up @@ -57,9 +57,8 @@ define i64 @sltiu(i64 %a) nounwind {
;
; RV32I-LABEL: sltiu:
; RV32I: # %bb.0:
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: sltiu a0, a0, 3
; RV32I-NEXT: snez a1, a1
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: ret
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40 changes: 21 additions & 19 deletions llvm/test/CodeGen/RISCV/double-convert.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -868,32 +868,33 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a3, 278016
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: li a2, -1
; RV32I-NEXT: call __gtdf2
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a3, 802304
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __fixdfdi
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: bgez s3, .LBB12_2
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv s4, a1
; RV32I-NEXT: lui s6, 524288
; RV32I-NEXT: bgez s2, .LBB12_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: lui s5, 524288
; RV32I-NEXT: lui s4, 524288
; RV32I-NEXT: .LBB12_2: # %start
; RV32I-NEXT: blez s2, .LBB12_4
; RV32I-NEXT: lui a3, 278016
; RV32I-NEXT: addi a3, a3, -1
; RV32I-NEXT: li a2, -1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __gtdf2
; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: blez a0, .LBB12_4
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: addi s5, a0, -1
; RV32I-NEXT: addi s4, s6, -1
; RV32I-NEXT: .LBB12_4: # %start
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
Expand All @@ -902,11 +903,11 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV32I-NEXT: call __unorddf2
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: slti a2, s3, 0
; RV32I-NEXT: and a1, a0, s4
; RV32I-NEXT: slti a2, s2, 0
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: and a2, a2, s4
; RV32I-NEXT: sgtz a3, s2
; RV32I-NEXT: and a2, a2, s3
; RV32I-NEXT: sgtz a3, s5
; RV32I-NEXT: neg a3, a3
; RV32I-NEXT: or a2, a3, a2
; RV32I-NEXT: and a0, a0, a2
Expand All @@ -917,6 +918,7 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down
5 changes: 2 additions & 3 deletions llvm/test/CodeGen/RISCV/forced-atomics.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3659,8 +3659,8 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind {
; RV32-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV32-NEXT: neg a3, a0
; RV32-NEXT: and a3, a3, a1
; RV32-NEXT: sw a4, 0(sp)
; RV32-NEXT: sw a1, 4(sp)
; RV32-NEXT: sw a4, 0(sp)
; RV32-NEXT: mv a1, sp
; RV32-NEXT: li a4, 5
; RV32-NEXT: li a5, 5
Expand All @@ -3672,8 +3672,7 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind {
; RV32-NEXT: .LBB52_2: # %atomicrmw.start
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: sltiu a0, a4, 2
; RV32-NEXT: snez a2, a1
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: seqz a2, a1
; RV32-NEXT: and a0, a2, a0
; RV32-NEXT: mv a2, a4
; RV32-NEXT: bnez a0, .LBB52_1
Expand Down
54 changes: 18 additions & 36 deletions llvm/test/CodeGen/RISCV/fpclamptosat.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -114,9 +114,8 @@ define i32 @utest_f64i32(double %x) {
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call __fixunsdfdi
; RV32IF-NEXT: seqz a1, a1
; RV32IF-NEXT: sltiu a2, a0, -1
; RV32IF-NEXT: snez a1, a1
; RV32IF-NEXT: addi a1, a1, -1
; RV32IF-NEXT: and a1, a1, a2
; RV32IF-NEXT: addi a1, a1, -1
; RV32IF-NEXT: or a0, a1, a0
Expand Down Expand Up @@ -430,9 +429,8 @@ define i32 @utesth_f16i32(half %x) {
; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: call __extendhfsf2
; RV32-NEXT: call __fixunssfdi
; RV32-NEXT: seqz a1, a1
; RV32-NEXT: sltiu a2, a0, -1
; RV32-NEXT: snez a1, a1
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: or a0, a1, a0
Expand Down Expand Up @@ -1229,10 +1227,8 @@ define i64 @utest_f64i64(double %x) {
; RV32IF-NEXT: lw a1, 20(sp)
; RV32IF-NEXT: lw a2, 12(sp)
; RV32IF-NEXT: lw a3, 8(sp)
; RV32IF-NEXT: seqz a4, a0
; RV32IF-NEXT: snez a5, a1
; RV32IF-NEXT: addi a5, a5, -1
; RV32IF-NEXT: and a4, a5, a4
; RV32IF-NEXT: or a4, a1, a0
; RV32IF-NEXT: seqz a4, a4
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: or a0, a0, a1
; RV32IF-NEXT: seqz a0, a0
Expand Down Expand Up @@ -1271,10 +1267,8 @@ define i64 @utest_f64i64(double %x) {
; RV32IFD-NEXT: lw a1, 20(sp)
; RV32IFD-NEXT: lw a2, 12(sp)
; RV32IFD-NEXT: lw a3, 8(sp)
; RV32IFD-NEXT: seqz a4, a0
; RV32IFD-NEXT: snez a5, a1
; RV32IFD-NEXT: addi a5, a5, -1
; RV32IFD-NEXT: and a4, a5, a4
; RV32IFD-NEXT: or a4, a1, a0
; RV32IFD-NEXT: seqz a4, a4
; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: or a0, a0, a1
; RV32IFD-NEXT: seqz a0, a0
Expand Down Expand Up @@ -1529,10 +1523,8 @@ define i64 @utest_f32i64(float %x) {
; RV32-NEXT: lw a1, 20(sp)
; RV32-NEXT: lw a2, 12(sp)
; RV32-NEXT: lw a3, 8(sp)
; RV32-NEXT: seqz a4, a0
; RV32-NEXT: snez a5, a1
; RV32-NEXT: addi a5, a5, -1
; RV32-NEXT: and a4, a5, a4
; RV32-NEXT: or a4, a1, a0
; RV32-NEXT: seqz a4, a4
; RV32-NEXT: xori a0, a0, 1
; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: seqz a0, a0
Expand Down Expand Up @@ -1780,10 +1772,8 @@ define i64 @utesth_f16i64(half %x) {
; RV32-NEXT: lw a1, 20(sp)
; RV32-NEXT: lw a2, 12(sp)
; RV32-NEXT: lw a3, 8(sp)
; RV32-NEXT: seqz a4, a0
; RV32-NEXT: snez a5, a1
; RV32-NEXT: addi a5, a5, -1
; RV32-NEXT: and a4, a5, a4
; RV32-NEXT: or a4, a1, a0
; RV32-NEXT: seqz a4, a4
; RV32-NEXT: xori a0, a0, 1
; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: seqz a0, a0
Expand Down Expand Up @@ -3083,10 +3073,8 @@ define i64 @utest_f64i64_mm(double %x) {
; RV32IF-NEXT: lw a1, 20(sp)
; RV32IF-NEXT: lw a2, 12(sp)
; RV32IF-NEXT: lw a3, 8(sp)
; RV32IF-NEXT: seqz a4, a0
; RV32IF-NEXT: snez a5, a1
; RV32IF-NEXT: addi a5, a5, -1
; RV32IF-NEXT: and a4, a5, a4
; RV32IF-NEXT: or a4, a1, a0
; RV32IF-NEXT: seqz a4, a4
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: or a0, a0, a1
; RV32IF-NEXT: seqz a0, a0
Expand Down Expand Up @@ -3125,10 +3113,8 @@ define i64 @utest_f64i64_mm(double %x) {
; RV32IFD-NEXT: lw a1, 20(sp)
; RV32IFD-NEXT: lw a2, 12(sp)
; RV32IFD-NEXT: lw a3, 8(sp)
; RV32IFD-NEXT: seqz a4, a0
; RV32IFD-NEXT: snez a5, a1
; RV32IFD-NEXT: addi a5, a5, -1
; RV32IFD-NEXT: and a4, a5, a4
; RV32IFD-NEXT: or a4, a1, a0
; RV32IFD-NEXT: seqz a4, a4
; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: or a0, a0, a1
; RV32IFD-NEXT: seqz a0, a0
Expand Down Expand Up @@ -3341,10 +3327,8 @@ define i64 @utest_f32i64_mm(float %x) {
; RV32-NEXT: lw a1, 20(sp)
; RV32-NEXT: lw a2, 12(sp)
; RV32-NEXT: lw a3, 8(sp)
; RV32-NEXT: seqz a4, a0
; RV32-NEXT: snez a5, a1
; RV32-NEXT: addi a5, a5, -1
; RV32-NEXT: and a4, a5, a4
; RV32-NEXT: or a4, a1, a0
; RV32-NEXT: seqz a4, a4
; RV32-NEXT: xori a0, a0, 1
; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: seqz a0, a0
Expand Down Expand Up @@ -3566,10 +3550,8 @@ define i64 @utesth_f16i64_mm(half %x) {
; RV32-NEXT: lw a1, 20(sp)
; RV32-NEXT: lw a2, 12(sp)
; RV32-NEXT: lw a3, 8(sp)
; RV32-NEXT: seqz a4, a0
; RV32-NEXT: snez a5, a1
; RV32-NEXT: addi a5, a5, -1
; RV32-NEXT: and a4, a5, a4
; RV32-NEXT: or a4, a1, a0
; RV32-NEXT: seqz a4, a4
; RV32-NEXT: xori a0, a0, 1
; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: seqz a0, a0
Expand Down
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