committed changes detailed in most recent edit of PR conversion

coffe/hardblock_functions.py

@@ -352,7 +352,7 @@ def write_pt_power_script(flow_settings,mode_enabled,clock_period,x):
   file.write("set search_path " + flow_settings['search_path'] + " \n")
   file.write("set my_top_level " + flow_settings['top_level'] + "\n")
   file.write("set my_clock_pin " + flow_settings['clock_pin_name'] + "\n")
-  file.write("set target_library " + flow_settings['target_library'] + "\n")
+  file.write("set target_library " + flow_settings['primetime_libs'] + "\n")
   file.write("set link_library " + flow_settings['link_library'] + "\n")
   file.write("read_verilog " + os.path.expanduser(flow_settings['pr_folder']) + "/netlist.v \n")
   file.write("link \n")
@@ -387,7 +387,7 @@ def write_pt_timing_script(flow_settings,mode_enabled,clock_period,x):
   file.write("set search_path " + flow_settings['search_path'] + " \n")
   file.write("set my_top_level " + flow_settings['top_level'] + "\n")
   file.write("set my_clock_pin " + flow_settings['clock_pin_name'] + "\n")
-  file.write("set target_library " + flow_settings['target_library'] + "\n")
+  file.write("set target_library " + flow_settings['primetime_libs'] + "\n")
   file.write("set link_library " + flow_settings['link_library'] + "\n")
   file.write("read_verilog " + os.path.expanduser(flow_settings['pr_folder']) + "/netlist.v \n")
   if mode_enabled and x <2**len(flow_settings['mode_signal']):
@@ -504,6 +504,7 @@ def flow_settings_pre_process(processed_flow_settings,cur_env):
   processed_flow_settings["best_case_libs"] = "\"" + " ".join(processed_flow_settings['best_case_libs']) + "\""
   processed_flow_settings["standard_libs"] = "\"" + " ".join(processed_flow_settings['standard_libs']) + "\""
   processed_flow_settings["worst_case_libs"] = "\"" + " ".join(processed_flow_settings['worst_case_libs']) + "\""
+  processed_flow_settings["primetime_libs"] = "\"" + " ".join(processed_flow_settings['primetime_libs']) + "\""
 
 # wire loads in the library are WireAreaLowkCon WireAreaLowkAgr WireAreaForZero
 def hardblock_flow(flow_settings): 

coffe/utils.py

@@ -697,6 +697,9 @@ def check_hard_params(hard_params,optional_params):
         if ((val == "" or val == -1 or val == -1.0 or val == []) and key not in optional_params):
             print("param \"%s\" is unset, please go to your hardblock/process params file and set it" % (key))
             sys.exit(1)
+        elif(key == "pnr_tool" and val != "encounter" and val != "innovus" ):
+            print("ERROR: pnr_tool must be set as either \"encounter\" or \"innovus\" ")
+            sys.exit(1)
 
 def load_hard_params(filename):
     """ Parse the hard block description file and load values into dictionary. 
@@ -743,7 +746,7 @@ def load_hard_params(filename):
         'space_around_core': -1,
         'pr_folder': "",
         #'primetime_lib_path': '',
-        #'primetime_lib_name': '',
+        'primetime_libs': [],
         'primetime_folder': "" ,
         'delay_cost_exp': 1.0,
         'area_cost_exp': 1.0,
@@ -766,6 +769,8 @@ def load_hard_params(filename):
         'mode_signal': [],
         'process_lib_paths': [],
         'process_params_file': "",
+        #'pnr_tool': "",
+        #'process_size': "",
     }
 
     hard_file = open(filename, 'r')
@@ -871,9 +876,15 @@ def load_hard_params(filename):
             hard_params['mode_signal'].append(value)
         elif param == "process_params_file":
             hard_params["process_params_file"] = value
+        # elif param == "pnr_tool":
+        #     hard_params["pnr_tool"] = value
+        # elif param == "process_size":
+        #     hard_params["process_size"] = value
         #To allow for the legacy way of inputting process specific params I'll keep these in (the only reason for having a seperate file is for understandability)
         if param == "process_lib_paths":
             hard_params["process_lib_paths"] = sanatize_str_input_to_list(value)
+        elif param == "primetime_libs":
+            hard_params["primetime_libs"] = sanatize_str_input_to_list(value)
         elif param == 'target_libraries':
             hard_params['target_libraries'] = sanatize_str_input_to_list(value)
         elif param == 'lef_files':
@@ -975,6 +986,8 @@ def load_hard_params(filename):
                 hard_params['pwr_pin'] = value.strip()
             elif param == 'wire_selection':
                 hard_params['wire_selection'].append(value)
+            elif param == "primetime_libs":
+                hard_params["primetime_libs"] = sanatize_str_input_to_list(value)
 
         process_param_file.close()
     #TODO make this more accessable outside of the code, but for now this is how I declare optional parameters

input_files/strtx_III_dsp/dsp_hb_settings.txt

@@ -25,7 +25,7 @@ process_params_file=input_files/strtx_III_dsp/process_specific_params.txt
 # Name of the clock pin in the design
 clock_pin_name=clk
 # Desired clock period in ns
-##clock_period=1.53
+#clock_period=1.53
 #clock_period=1.66
 #clock_period=1.81
 clock_period=2.0
@@ -70,13 +70,14 @@ target_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_En
 
 # Libraries required in EDI:
 
+#metal_layers=9
 #metal_layers=8
 #metal_layers=7
 #metal_layers=6
 #metal_layers=5
 
 #names of metal layers starting from the bottom-most layer on the left. use a python list format. 
-#metal_layer_names=["M1", "M2", "M3", "M4", "M5", "M6", "M7", "AP"]
+#metal_layer_names=["M1", "M2", "M3", "M4", "M5", "M6", "M7", "M8", "M9","AP"]
 
 #names of metal layers to use for each side of the power ring
 #order: top, bottom, left, right
@@ -132,7 +133,7 @@ power_ring_width=3
 power_ring_spacing=3
 height_to_width_ratio=4.0
 
-space_around_core=5
+space_around_core=10
 
 # The folder in which place and route reports and post-routing netlists and spef files will be stored
 pr_folder=~/COFFE/output_files/strtx_III_dsp/pr
@@ -141,8 +142,8 @@ pr_folder=~/COFFE/output_files/strtx_III_dsp/pr
 ########## Prime Time Settings ###############
 ##############################################
 
-mode_signal=mode_0
-mode_signal=mode_1
+#mode_signal=mode_0
+#mode_signal=mode_1
 
 primetime_folder=~/COFFE/output_files/strtx_III_dsp/pt
 

input_files/strtx_III_dsp/process_specific_params.txt

@@ -3,10 +3,15 @@
 #############################################
 ############# ASIC Flow Settings ############
 #############################################
+#node size of process in nm
+#process_size=65
+
 process_lib_paths="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c"
 
+########################################
+########## Synthesis Settings ##########
+########################################
 # Standard cell libs which we are targeting for synthesis
-
 target_libraries="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gpluswc.db /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2wc.db"
 
 ##############################################
@@ -23,13 +28,14 @@ best_case_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/
 standard_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gplustc.lib /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2tc.lib"
 worst_case_libs="/CMC/kits/tsmc_65nm_libs/tcbn65gplus/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn65gplus_140b/tcbn65gpluswc.lib /CMC/kits/tsmc_65nm_libs/tpzn65gpgv2/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpzn65gpgv2_140c/tpzn65gpgv2wc.lib"
 
+
 #metal_layers=8
 metal_layers=7
 #metal_layers=6
 #metal_layers=5
 
 #names of metal layers starting from the bottom-most layer on the left. use a python list format. 
-metal_layer_names=["M1", "M2", "M3", "M4", "M5", "M6", "M7", "AP"]
+metal_layer_names=["M1", "M2", "M3", "M4", "M5", "M6", "M7", "M8", "M9", "AP"]
 
 #names of metal layers to use for each side of the power ring
 #order: top, bottom, left, right
@@ -60,3 +66,10 @@ filler_cell_names=["FILL1", "FILL16", "FILL1_LL", "FILL2", "FILL32", "FILL64", "
 
 #name of the core site in the floorplan. can be obtained from lef files.
 core_site_name=core
+
+
+##############################################
+############## Power & Timing ################
+##############################################
+
+primetime_libs="tcbn65gpluswc.db tpzn65gpgv2wc.db"

unit_test.sh

@@ -5,8 +5,8 @@ py2=$(which python2)
 py3=$(which python3)
 if [ $py2 != "" ] || [ $py3 != "" ] 
 then
-    #run the coffe flow
-    python2 coffe.py -ho -i 1 input_files/strtx_III_dsp/dsp_coffe_params.txt
+    #run the coffe flow, hardblock and full custom
+    python2 coffe.py -i 1 input_files/strtx_III_dsp/dsp_coffe_params.txt
     cd ./analyze_results
     python3 condense_reports.py -r ../output_files/strtx_III_dsp/arch_out_dir
     python3 plot_coffe_results.py -c report_csv_out/condensed_report.csv