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Whitespacefix #4

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Whitespacefix #4

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3eff480
[config] Fix help string
wallento Jan 25, 2019
3717ed9
[structure] Rename SystemVerilog to sv
wallento Jan 25, 2019
091e09b
[structure] Move types to package
wallento Jan 27, 2019
46f61f5
Whitespace fixes
wallento Jan 27, 2019
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2 changes: 1 addition & 1 deletion configs/swerv.config
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Original file line number Diff line number Diff line change
Expand Up @@ -99,7 +99,7 @@ User options:

Additional direct options for the following variables:

-ret_size = {2, 3, 4, ... 8}
-ret_stack_size = {2, 3, 4, ... 8}
size of return stack
-btb_size = { 32, 48, 64, 128, 256, 512 }
size of branch target buffer
Expand Down
272 changes: 136 additions & 136 deletions design/dbg/dbg.sv
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68 changes: 34 additions & 34 deletions design/dec/cdecode
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Original file line number Diff line number Diff line change
Expand Up @@ -116,7 +116,7 @@ c.swsp = [110...........10]
c.xor = [100011...01...01]


.input
.input
rv32c = {
i[15]
i[14]
Expand Down Expand Up @@ -159,38 +159,38 @@ rv32c = {
uimm5_0
uswimm6_2
uswspimm7_2
o[31]
o[30]
o[29]
o[28]
o[27]
o[26]
o[25]
o[24]
o[23]
o[22]
o[21]
o[20]
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o[11]
o[10]
o[9]
o[8]
o[7]
o[6]
o[5]
o[4]
o[3]
o[2]
o[1]
o[0]
o[31]
o[30]
o[29]
o[28]
o[27]
o[26]
o[25]
o[24]
o[23]
o[22]
o[21]
o[20]
o[19]
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o[16]
o[15]
o[14]
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o[12]
o[11]
o[10]
o[9]
o[8]
o[7]
o[6]
o[5]
o[4]
o[3]
o[2]
o[1]
o[0]
}

# assign rs2d[4:0] = i[6:2];
Expand All @@ -199,7 +199,7 @@ rv32c = {
#
# assign rdpd[4:0] = {2'b01, i[9:7]};
#
# assign rs2pd[4:0] = {2'b01, i[4:2]};
# assign rs2pd[4:0] = {2'b01, i[4:2]};

.decode

Expand Down
48 changes: 24 additions & 24 deletions design/dec/csrdecode
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Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,7 @@ csr_perfvg = [001100100111]
csr_perfvh = [001100101...]
csr_perfvi = [00110011....]

.input
.input

csr = {
dec_csr_rdaddr_d[11]
Expand All @@ -87,23 +87,23 @@ csr = {
.output

csr = {
csr_misa
csr_mvendorid
csr_marchid
csr_mimpid
csr_mhartid
csr_mstatus
csr_mtvec
csr_mip
csr_mie
csr_mcyclel
csr_mcycleh
csr_minstretl
csr_minstreth
csr_mscratch
csr_mepc
csr_mcause
csr_mtval
csr_misa
csr_mvendorid
csr_marchid
csr_mimpid
csr_mhartid
csr_mstatus
csr_mtvec
csr_mip
csr_mie
csr_mcyclel
csr_mcycleh
csr_minstretl
csr_minstreth
csr_mscratch
csr_mepc
csr_mcause
csr_mtval
csr_mrac
csr_dmst
csr_mdeau
Expand All @@ -120,8 +120,8 @@ csr = {
csr_mcpc
csr_mfdc
csr_dpc
csr_mtsel
csr_mtdata1
csr_mtsel
csr_mtdata1
csr_mtdata2
csr_mhpmc3
csr_mhpmc4
Expand Down Expand Up @@ -211,10 +211,10 @@ csr[ csr_mhpme6 ] = { csr_mhpme6 }
csr[ csr_micect ] = { csr_micect }
csr[ csr_miccmect ] = { csr_miccmect }
csr[ csr_mdccmect ] = { csr_mdccmect }
csr[ csr_dicawics ] = { csr_dicawics }
csr[ csr_dicad0 ] = { csr_dicad0 }
csr[ csr_dicad1 ] = { csr_dicad1 }
csr[ csr_dicago ] = { csr_dicago }
csr[ csr_dicawics ] = { csr_dicawics }
csr[ csr_dicad0 ] = { csr_dicad0 }
csr[ csr_dicad1 ] = { csr_dicad1 }
csr[ csr_dicago ] = { csr_dicago }

csr[ csr_perfva ] = { valid_only }
csr[ csr_perfvb ] = { valid_only }
Expand Down
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