August 2024 Release

1. Support 4 CPU cores on QEMU.

2. Add a terminal server so that processes on different cores can print concurrently.

3. Switch to the LiteX+VexRiscv framework on the FPGA boards, which enables

• page table translation code running on both QEMU and the boards;
• access to the Ethernet port on the boards, leading to a kernel-bypass networking application;
• 256MB memory (much larger than before) so that every struct process can hold a message buffer for system call.

Note that support for the Arty S7 board is temporarily suspended. We will add this support back later, but Arty S7 does not have an Ethernet port.

May 2024 Release

Support the SD drive emulation in QEMU.

Support the official QEMU and the official GNU C compiler.

Support the mriscv open-sourced processor in System Verilog.

Improve the use of types and the assembly code for trap entry.

August 2023 Release

Add support for the Arty S7-50 and Arty A7-100t boards.

Add the non-preemptive multi-threading project to apps/user.

Add support for the processor from ECE4750 which is a pipelined RISC-V processor in Verilog.

December 2022 Release

Add skeleton code for the page table translation project.

Separate the code of paging device from the code of memory management.

Cleanup the code and improve the documents.

October 2022 Release

Add QEMU support so that the Arty board becomes optional.

Add page table translation with the help of QEMU.

Add tutorial video for MacOS users.

May 2022 Release

Add tutorial video for Windows users.

Add skeleton code for memory protection and exception project.

Remove RISC-V extensions mac from compiler flag so that egos-2000 only uses the basic rv32i, making it easier to run on students' own processor design.

Initial Release

This is the initial release of egos-2000 before receiving comments and suggestions from the public.

Please refer to references/USAGES.md for programming the bootROM to the Arty board and the disk image to the microSD card.