GPRs modification

[mlabaf2]

Before start

• I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集相关的问题。
• I have read the XiangShan Documents. 我已经阅读过香山文档。
• I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
• I have searched the previous discussions and did not find anything relevant. 我已经搜索过之前的 discussions，并没有找到相关的。
• I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。

Describe the question

Hi
I want to extent length of GPRs registers to 128 or 129 bits (especially register files for integer section) but I cannot find where is the definition in Xiangshan code, Yanqihu ?
Also, I cannot find how GPRs are connected to FunctionUnitInput and FuOutput in functionUnit.scala?
thank you for the response

[cebarobot]

Fisrt question

Fisrt of all, Yanqihu is not in maintenance currently and we cannot give to much support.

For Yanqihu (branch yanqihu or tag v1.0)

There is an len parameter in class Regfile (src/main/scala/xiangshan/backend/regfile/Regfile.scala).

XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala

Lines 54 to 60 in d7c2b43

	class Regfile
	(
	numReadPorts: Int,
	numWirtePorts: Int,
	hasZero: Boolean,
	len: Int
	) extends XSModule {

len is decided by XLEN in class IntegerBlock (src/main/scala/xiangshan/backend/IntegerBlock.scala)

XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala

Lines 148 to 153 in 2979cba

	val intRf = Module(new Regfile(
	numReadPorts = NRIntReadPorts,
	numWirtePorts = NRIntWritePorts,
	hasZero = true,
	len = XLEN
	))

Also, class Regfile used an verilog module regfile_160x64_10w16r_sim (src/main/resources/vsrc/regfile_160x64_10w16r_sim.v) for memory. You may also modifiy this.

For Kunminghu (branch master)

In Regfile.scala you could found a class Regfile and an object Regfile. You could find that the width of class Regfile is defined by dataBits in object Regfile, which is defined by the width of wdata IO port when applying object Regfile.

XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala

Lines 157 to 164 in ddab25a

	val dataBits = wdata.map(_.getWidth).min
	require(wdata.map(_.getWidth).min == wdata.map(_.getWidth).max, s"dataBits != $dataBits")
	val addrBits = waddr.map(_.getWidth).min
	require(waddr.map(_.getWidth).min == waddr.map(_.getWidth).max, s"addrBits != $addrBits")
	val instanceName = name(0).toLower.toString() + name.drop(1)
	require(instanceName != name, "Regfile Instance Name can't be same as Module name")
	val regfile = Module(new Regfile(name, numEntries, numReadPorts, numWritePorts, hasZero, dataBits, addrBits, bankNum, isVlRegfile)).suggestName(instanceName)

You may have to modified the whole datapath to extend the width.

Second question

In yanqihu, There seems to be no FunctionUnitInput.

In master XiangShan, FunctionUnit, as well as FunctionUnitInput and FuOutput, are deprecated and replaced by FuncUnit.

[mlabaf2]

thanks for the response