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Pull requests: OpenXiangShan/XiangShan
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area(VirtualLoadQueue): remove useless regs
area
Optimize area comsuption
#4061
opened Dec 18, 2024 by
cz4e
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fix(LoadPipe): enable s1 permission check at s1 in LoadPipe for prefetch_w
#4056
opened Dec 17, 2024 by
cz4e
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area(CacheOpDecoder): remove CacheOpDecoder
area
Optimize area comsuption
#4050
opened Dec 16, 2024 by
cz4e
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ppa(backend)
do not merge
Do not merge this pull request
#4049
opened Dec 16, 2024 by
xiaofeibao-xjtu
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submodule: bump submodule yunsuan, rocket-chip, and ready-to-run
#4040
opened Dec 13, 2024 by
NewPaulWalker
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style(MainPipe): remove duplicate signals
do not merge
Do not merge this pull request
#4035
opened Dec 12, 2024 by
cz4e
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submodule(utility), transforms: collect XSLogs to SimTop.LogPerfEndpoint
#3982
opened Dec 4, 2024 by
klin02
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area(csr): fix intr NO bits and remove reg for waddr/wdata
#3970
opened Dec 2, 2024 by
sinceforYy
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ci: use Do not merge this pull request
KunminghuV2Config
except perf
do not merge
#3969
opened Dec 2, 2024 by
Tang-Haojin
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fix(intr): support non-mmio load-store instructions to trigger interrupts
do not merge
Do not merge this pull request
#3938
opened Nov 26, 2024 by
sinceforYy
•
Draft
Power frontend dyn close sc
do not merge
Do not merge this pull request
power
about power design or optimization
#3911
opened Nov 21, 2024 by
Lawrence-ID
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