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ppa(backend) #4049

Merged
merged 32 commits into from
Dec 19, 2024
Merged

ppa(backend) #4049

merged 32 commits into from
Dec 19, 2024

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xiaofeibao-xjtu
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@xiaofeibao-xjtu xiaofeibao-xjtu added the do not merge Do not merge this pull request label Dec 16, 2024
@xiaofeibao-xjtu xiaofeibao-xjtu changed the title tmp backend ppa ppa(backend) Dec 16, 2024
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[Generated by IPC robot]
commit: e43f9ac

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
e43f9ac 1.886 0.443 2.641 1.226 2.157 2.150 2.362 0.946 1.414 1.998 3.114 2.557 2.303 3.311

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
042e89e 1.952 0.439 2.696 1.228 2.847 2.457 2.366 0.933 1.400 1.979 3.418 2.726 2.383 3.272
729ce9e 1.952 0.439 2.696 1.228 2.847 2.457 2.366 0.933 1.400 1.979 3.418 2.726 2.383 3.272
72001a1
7a5c0ba 1.952 0.439 2.696 1.228 2.847 2.457 2.366 0.933 1.400 1.979 3.418 2.726 2.383 3.272
72dab97 1.952 0.439 2.696 1.228 2.847 2.457 2.366 0.933 1.400 1.979 3.418 2.727 2.383 3.272

@xiaofeibao-xjtu @Anzooooo
feat(backend): NewDispatch
0725276
@xiaofeibao-xjtu @Anzooooo
area(backend): reduce 4 fexu to 3 fexu
84e8100
@xiaofeibao-xjtu @Anzooooo
area(Backend): merge pcMem and pcTargetMem
6a1210d
@xiaofeibao-xjtu @Anzooooo
area(backend): remove memCtrl and disble mdp
4a8537f
@xiaofeibao-xjtu @Anzooooo
area(Backend): reduce VfScheduler iq num from 3 to 2 and remove a vfc…
93d3c27 
…vt fu
@xiaofeibao-xjtu @Anzooooo
timing(backend): pipe robCommits for better timing and area
2f6b6d0
@xiaofeibao-xjtu @Anzooooo
Revert "area(Backend): reduce VfScheduler iq num from 3 to 2 and remo…
3e64deb 
…ve a vfcvt fu"

This reverts commit 10b44fa68ead2a8d79ce215b6bb116912f72f3a4.
@xiaofeibao-xjtu @Anzooooo
area(backend): reduce a vfcvt for better area
2e6fb1b
@xiaofeibao-xjtu @Anzooooo
area(backend): only pipe wakeupFromIQ and wakeupFromWB once
e2bf2ed
@xiaofeibao-xjtu @Anzooooo
area(backend): only use startAddr in pcMem
1498053
@xiaofeibao-xjtu @Anzooooo
timing(rob): enqRob pipe for better timing
13ac068
@xiaofeibao-xjtu @Anzooooo
timing(jumpUnit): fix target timing
5878755
@xiaofeibao-xjtu @Anzooooo
timing(redirectGen): fix timing of addr trans type exception
c938f7d
@xiaofeibao-xjtu @Anzooooo
fix(rob): fix bug of canAcceptForDispatch
2c7f1c8
@xiaofeibao-xjtu @Anzooooo
area(exu): ctrl signals only pipe once in exu
60a5beb
@xiaofeibao-xjtu @Anzooooo
timing(intRegfile): use IntRegFileSplit for better timing
f94811c
@xiaofeibao-xjtu @Anzooooo
timing(DecodeUnit): remove fpToVecDecoder
baad73f
@xiaofeibao-xjtu @Anzooooo
area(exu): data signals only pipe once in exu
e31c5cb
@xiaofeibao-xjtu @Anzooooo
timing(backend): each IQ has at least two simple entries
5f0b975
@xiaofeibao-xjtu @Anzooooo
fix(pcmem): add read target from newestEntryTarget
3d1dc29
@xiaofeibao-xjtu @Anzooooo
fix(decode): scala fp fu's fmt use fpuCtrl instead of vsew
a79b124
xiaofeibao-xjtu and others added 9 commits December 17, 2024 18:23
@xiaofeibao-xjtu @Anzooooo
fix(ctrlBlock): fix bug of useSnpt when only flag diffrence
ee2f6cd
@xiaofeibao-xjtu @Anzooooo
timing(vldMgu): fix timing of wbReg's gate enable
8593f2a
@xiaofeibao-xjtu @Anzooooo
area(intRegFile): change intRegFile splitNum to 4
10c8cfe
@NewPaulWalker @Anzooooo
timing(zacas): move isDropAmocasSta logic gen from Scheduler to NewDi…
293a3b8 
…spatch
@xiaofeibao-xjtu @Anzooooo
fix(dispatch): fix bug of index vld instr, each uop can be index vld …
1250f7e 
…instr
@wissygh @Anzooooo
area(trace, pcMem): Trace only get startAddr from pcmem
cd88eb7
@xiaofeibao-xjtu @Anzooooo
fix(scheduler): fix bug of sta valid
ecdf2e8
@xiaofeibao-xjtu @Anzooooo
fix(dispatch): fix bug of hasException's instr send to iq
2898290
@Anzooooo
fix(LSQ): modify the enq logic
3932d10 
This commit modifies the previous silly queue entry.
This greatly reduces the generated verilog, making:
StoreQueue verilog in StoreQueue from 26W lines -> 5W lines
verilog in VirtualLoadQueue from 13W lines -> 2W lines

Also, we can no longer limit the number of numLsElem per `io.enq`.
@Anzooooo Anzooooo requested a review from linjuanZ December 17, 2024 12:51
@Anzooooo
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Anzooooo commented Dec 17, 2024 •
edited
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This commit(3932d10) modifies LSQ's previous method of queue entry.

Also, we can no longer limit the number of numLsElem per io.enq.

Also, I removed the reg that should have been removed that I missed in the previous StoreQueue:

XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala

Line 815 in 3932d10

uncacheUop.trigger := 0.U.asTypeOf(TriggerAction())

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[Generated by IPC robot]
commit: c83a1b7

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
c83a1b7 1.886 0.443 2.642 1.226 2.157 2.150 2.362 0.946 1.414 1.998 3.114 2.557 2.303 3.311

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
a6696f0 1.952 0.439 2.696 1.228 2.847 2.457 2.366 0.933 1.400 1.979 3.418 2.726 2.383 3.272
c092d57 1.952 0.439 2.696 1.228 2.847 2.457 2.366 0.933 1.400 1.979 3.418 2.726 2.383 3.272
0ae34b3 1.952 0.439 2.696 1.228 2.847 2.457 2.366 0.933 1.400 1.979 3.418 2.726 2.383 3.272
042e89e 1.952 0.439 2.696 1.228 2.847 2.457 2.366 0.933 1.400 1.979 3.418 2.726 2.383 3.272
729ce9e 1.952 0.439 2.696 1.228 2.847 2.457 2.366 0.933 1.400 1.979 3.418 2.726 2.383 3.272

@xiaofeibao-xjtu xiaofeibao-xjtu removed the do not merge Do not merge this pull request label Dec 19, 2024
@Tang-Haojin Tang-Haojin merged commit 2e4f14f into master Dec 19, 2024
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@Tang-Haojin Tang-Haojin deleted the tmp-backend-ppa branch December 19, 2024 10:03
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@cz4e cz4e Awaiting requested review from cz4e cz4e is a code owner

@good-circle good-circle Awaiting requested review from good-circle good-circle is a code owner

@linjuanZ linjuanZ Awaiting requested review from linjuanZ linjuanZ is a code owner

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7 participants
@xiaofeibao-xjtu @XiangShanRobot @Anzooooo @linjuanZ @Tang-Haojin @NewPaulWalker @wissygh