Code

ppa(backend)#4049

Code

Merged

Tang-Haojin merged 32 commits intomasterOpenXiangShan/XiangShan:masterfrom tmp-backend-ppaOpenXiangShan/XiangShan:tmp-backend-ppaCopy head branch name to clipboardDec 19, 2024

+1,739-1,296

Commits

Commits on Dec 17, 2024

• feat(backend): NewDispatch

  

  xiaofeibao-xjtu

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  0725276

• area(backend): reduce 4 fexu to 3 fexu

  

  xiaofeibao-xjtu

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  84e8100

• area(Backend): merge pcMem and pcTargetMem

  

  xiaofeibao-xjtu

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  6a1210d

• area(backend): remove memCtrl and disble mdp

  

  xiaofeibao-xjtu

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  4a8537f

• area(Backend): reduce VfScheduler iq num from 3 to 2 and remove a vfcvt fu

  

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  93d3c27

• timing(backend): pipe robCommits for better timing and area

  

  xiaofeibao-xjtu

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  2f6b6d0

• Revert "area(Backend): reduce VfScheduler iq num from 3 to 2 and remove a vfcvt fu"

  Show description for 3e64deb
  

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  3e64deb

• area(backend): reduce a vfcvt for better area

  

  xiaofeibao-xjtu

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  2e6fb1b

• area(backend): only pipe wakeupFromIQ and wakeupFromWB once

  

  xiaofeibao-xjtu

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  e2bf2ed

• area(backend): only use startAddr in pcMem

  

  xiaofeibao-xjtu

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  1498053

• timing(rob): enqRob pipe for better timing

  

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  13ac068

• timing(jumpUnit): fix target timing

  

  xiaofeibao-xjtu

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  5878755

• timing(redirectGen): fix timing of addr trans type exception

  

  xiaofeibao-xjtu

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  c938f7d

• fix(rob): fix bug of canAcceptForDispatch

  

  xiaofeibao-xjtu

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  2c7f1c8

• area(exu): ctrl signals only pipe once in exu

  

  xiaofeibao-xjtu

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  60a5beb

• timing(intRegfile): use IntRegFileSplit for better timing

  

  xiaofeibao-xjtu

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  f94811c

• timing(DecodeUnit): remove fpToVecDecoder

  

  xiaofeibao-xjtu

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  baad73f

• area(exu): data signals only pipe once in exu

  

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  e31c5cb

• timing(backend): each IQ has at least two simple entries

  

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  5f0b975

• fix(pcmem): add read target from newestEntryTarget

  

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  3d1dc29

• fix(decode): scala fp fu's fmt use fpuCtrl instead of vsew

  

  xiaofeibao-xjtu

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  a79b124

• fix(ctrlBlock): fix bug of useSnpt when only flag diffrence

  

  xiaofeibao-xjtu

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  ee2f6cd

• timing(vldMgu): fix timing of wbReg's gate enable

  

  xiaofeibao-xjtu

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  8593f2a

• area(intRegFile): change intRegFile splitNum to 4

  

  xiaofeibao-xjtu

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  10c8cfe

• timing(zacas): move isDropAmocasSta logic gen from Scheduler to NewDispatch

  

  NewPaulWalker

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  293a3b8

• fix(dispatch): fix bug of index vld instr, each uop can be index vld instr

  

  xiaofeibao-xjtu

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  1250f7e

• area(trace, pcMem): Trace only get startAddr from pcmem

  

  wissygh

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  cd88eb7

• fix(scheduler): fix bug of sta valid

  

  xiaofeibao-xjtu

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  ecdf2e8

• fix(dispatch): fix bug of hasException's instr send to iq

  

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  2898290

• fix(LSQ): modify the enq logic

  Show description for 3932d10
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  3932d10

Commits on Dec 18, 2024

• fix(fpDecoder): fix bug of fmt

  xiaofeibao-xjtu

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  4137128

• fix(rob): fix bug of redirect when all robEntries need flush

  xiaofeibao-xjtu

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  c83a1b7