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ppa(backend) #4049

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merged 32 commits into from
Dec 19, 2024
Merged

ppa(backend) #4049

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0725276
feat(backend): NewDispatch
xiaofeibao-xjtu Nov 22, 2024
84e8100
area(backend): reduce 4 fexu to 3 fexu
xiaofeibao-xjtu Nov 22, 2024
6a1210d
area(Backend): merge pcMem and pcTargetMem
xiaofeibao-xjtu Nov 25, 2024
4a8537f
area(backend): remove memCtrl and disble mdp
xiaofeibao-xjtu Nov 26, 2024
93d3c27
area(Backend): reduce VfScheduler iq num from 3 to 2 and remove a vfc…
xiaofeibao-xjtu Nov 26, 2024
2f6b6d0
timing(backend): pipe robCommits for better timing and area
xiaofeibao-xjtu Nov 28, 2024
3e64deb
Revert "area(Backend): reduce VfScheduler iq num from 3 to 2 and remo…
xiaofeibao-xjtu Nov 29, 2024
2e6fb1b
area(backend): reduce a vfcvt for better area
xiaofeibao-xjtu Nov 29, 2024
e2bf2ed
area(backend): only pipe wakeupFromIQ and wakeupFromWB once
xiaofeibao-xjtu Dec 2, 2024
1498053
area(backend): only use startAddr in pcMem
xiaofeibao-xjtu Dec 2, 2024
13ac068
timing(rob): enqRob pipe for better timing
xiaofeibao-xjtu Dec 4, 2024
5878755
timing(jumpUnit): fix target timing
xiaofeibao-xjtu Dec 4, 2024
c938f7d
timing(redirectGen): fix timing of addr trans type exception
xiaofeibao-xjtu Dec 5, 2024
2c7f1c8
fix(rob): fix bug of canAcceptForDispatch
xiaofeibao-xjtu Dec 5, 2024
60a5beb
area(exu): ctrl signals only pipe once in exu
xiaofeibao-xjtu Dec 8, 2024
f94811c
timing(intRegfile): use IntRegFileSplit for better timing
xiaofeibao-xjtu Dec 9, 2024
baad73f
timing(DecodeUnit): remove fpToVecDecoder
xiaofeibao-xjtu Dec 9, 2024
e31c5cb
area(exu): data signals only pipe once in exu
xiaofeibao-xjtu Dec 10, 2024
5f0b975
timing(backend): each IQ has at least two simple entries
xiaofeibao-xjtu Dec 10, 2024
3d1dc29
fix(pcmem): add read target from newestEntryTarget
xiaofeibao-xjtu Dec 11, 2024
a79b124
fix(decode): scala fp fu's fmt use fpuCtrl instead of vsew
xiaofeibao-xjtu Dec 12, 2024
ee2f6cd
fix(ctrlBlock): fix bug of useSnpt when only flag diffrence
xiaofeibao-xjtu Dec 15, 2024
8593f2a
timing(vldMgu): fix timing of wbReg's gate enable
xiaofeibao-xjtu Dec 15, 2024
10c8cfe
area(intRegFile): change intRegFile splitNum to 4
xiaofeibao-xjtu Dec 15, 2024
293a3b8
timing(zacas): move isDropAmocasSta logic gen from Scheduler to NewDi…
NewPaulWalker Dec 16, 2024
1250f7e
fix(dispatch): fix bug of index vld instr, each uop can be index vld …
xiaofeibao-xjtu Dec 16, 2024
cd88eb7
area(trace, pcMem): Trace only get `startAddr` from pcmem
wissygh Dec 16, 2024
ecdf2e8
fix(scheduler): fix bug of sta valid
xiaofeibao-xjtu Dec 16, 2024
2898290
fix(dispatch): fix bug of hasException's instr send to iq
xiaofeibao-xjtu Dec 16, 2024
3932d10
fix(LSQ): modify the enq logic
Anzooooo Dec 17, 2024
4137128
fix(fpDecoder): fix bug of fmt
xiaofeibao-xjtu Dec 17, 2024
c83a1b7
fix(rob): fix bug of redirect when all robEntries need flush
xiaofeibao-xjtu Dec 18, 2024
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9 changes: 0 additions & 9 deletions src/main/scala/xiangshan/Bundle.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -167,19 +167,10 @@ class CtrlFlow(implicit p: Parameters) extends XSBundle {


class FPUCtrlSignals(implicit p: Parameters) extends XSBundle {
val isAddSub = Bool() // swap23
val typeTagIn = UInt(2.W) // H S D
val typeTagOut = UInt(2.W) // H S D
val fromInt = Bool()
val wflags = Bool()
val fpWen = Bool()
val fmaCmd = UInt(2.W)
val div = Bool()
val sqrt = Bool()
val fcvt = Bool()
val typ = UInt(2.W)
val fmt = UInt(2.W)
val ren3 = Bool() //TODO: remove SrcType.fp
val rm = UInt(3.W)
}

Expand Down
71 changes: 29 additions & 42 deletions src/main/scala/xiangshan/Parameters.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -229,7 +229,7 @@ case class XSCoreParameters
VecMemDispatchWidth: Int = 1,
VecMemDispatchMaxNumber: Int = 16,
VecMemUnitStrideMaxFlowNum: Int = 2,
VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2),
VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 16, 16, 16, 16, 16),
StoreBufferSize: Int = 16,
StoreBufferThreshold: Int = 7,
EnsbufferWidth: Int = 2,
Expand Down Expand Up @@ -410,7 +410,7 @@ case class XSCoreParameters
), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
IssueBlockParams(Seq(
ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2),
ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))),
ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 2, 1)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))),
), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize),
IssueBlockParams(Seq(
ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2),
Expand All @@ -430,20 +430,15 @@ case class XSCoreParameters
SchdBlockParams(Seq(
IssueBlockParams(Seq(
ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))),
), numEntries = 18, numEnq = 2, numComp = 16),
ExeUnitParams("FEX1", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))),
), numEntries = 18, numEnq = 2, numComp = 14),
IssueBlockParams(Seq(
ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))),
), numEntries = 18, numEnq = 2, numComp = 16),
ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))),
ExeUnitParams("FEX3", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(9, 1)))),
), numEntries = 18, numEnq = 2, numComp = 14),
IssueBlockParams(Seq(
ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))),
), numEntries = 18, numEnq = 2, numComp = 16),
IssueBlockParams(Seq(
ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))),
), numEntries = 18, numEnq = 2, numComp = 16),
IssueBlockParams(Seq(
ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))),
ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))),
), numEntries = 18, numEnq = 2, numComp = 16),
ExeUnitParams("FEX4", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 1)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))),
), numEntries = 18, numEnq = 2, numComp = 14),
),
numPregs = fpPreg.numEntries,
numDeqOutside = 0,
Expand All @@ -459,14 +454,14 @@ case class XSCoreParameters
IssueBlockParams(Seq(
ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))),
ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))),
), numEntries = 16, numEnq = 2, numComp = 14),
), numEntries = 16, numEnq = 2, numComp = 12),
IssueBlockParams(Seq(
ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))),
ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))),
), numEntries = 16, numEnq = 2, numComp = 14),
ExeUnitParams("VFEX3", Seq(VfaluCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))),
), numEntries = 16, numEnq = 2, numComp = 12),
IssueBlockParams(Seq(
ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))),
), numEntries = 10, numEnq = 2, numComp = 8),
), numEntries = 10, numEnq = 2, numComp = 6),
),
numPregs = vfPreg.numEntries,
numDeqOutside = 0,
Expand All @@ -483,31 +478,31 @@ case class XSCoreParameters
SchdBlockParams(Seq(
IssueBlockParams(Seq(
ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))),
), numEntries = 16, numEnq = 1, numComp = 15),
), numEntries = 16, numEnq = 2, numComp = 12),
IssueBlockParams(Seq(
ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))),
), numEntries = 16, numEnq = 1, numComp = 15),
), numEntries = 16, numEnq = 2, numComp = 12),
IssueBlockParams(Seq(
ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(8, 0))), true, 2),
), numEntries = 16, numEnq = 1, numComp = 15),
ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(3, 0)), Seq(Seq(IntRD(8, 0))), true, 2),
), numEntries = 16, numEnq = 2, numComp = 12),
IssueBlockParams(Seq(
ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(9, 0))), true, 2),
), numEntries = 16, numEnq = 1, numComp = 15),
ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(4, 0)), Seq(Seq(IntRD(9, 0))), true, 2),
), numEntries = 16, numEnq = 2, numComp = 12),
IssueBlockParams(Seq(
ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(10, 0))), true, 2),
), numEntries = 16, numEnq = 1, numComp = 15),
ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(5, 0)), Seq(Seq(IntRD(10, 0))), true, 2),
), numEntries = 16, numEnq = 2, numComp = 12),
IssueBlockParams(Seq(
ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0), VlWB(port = 2, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))),
), numEntries = 16, numEnq = 1, numComp = 15),
), numEntries = 16, numEnq = 2, numComp = 12),
IssueBlockParams(Seq(
ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0), VlWB(port = 3, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))),
), numEntries = 16, numEnq = 1, numComp = 15),
), numEntries = 16, numEnq = 2, numComp = 12),
IssueBlockParams(Seq(
ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(12, 0)))),
), numEntries = 16, numEnq = 1, numComp = 15),
ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(9, 0)))),
), numEntries = 16, numEnq = 2, numComp = 12),
IssueBlockParams(Seq(
ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(13, 0)))),
), numEntries = 16, numEnq = 1, numComp = 15),
ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(10, 0)))),
), numEntries = 16, numEnq = 2, numComp = 12),
),
numPregs = intPreg.numEntries max vfPreg.numEntries,
numDeqOutside = 0,
Expand All @@ -527,17 +522,9 @@ case class XSCoreParameters
),
// TODO: add load -> fp slow wakeup
WakeUpConfig(
Seq("FEX0", "FEX1", "FEX2", "FEX3") ->
Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5")
),
WakeUpConfig(
Seq("FEX0", "FEX1", "FEX2", "FEX3") ->
Seq("STD0", "STD1")
Seq("FEX0", "FEX2", "FEX4") ->
Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4")
),
// WakeUpConfig(
// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") ->
// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3")
// ),
).flatten
}

Expand Down
1 change: 0 additions & 1 deletion src/main/scala/xiangshan/XSCore.scala
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Expand Up @@ -195,7 +195,6 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)

// By default, instructions do not have exceptions when they enter the function units.
memBlock.io.ooo_to_mem.issueUops.map(_.bits.uop.clearExceptions())
memBlock.io.ooo_to_mem.loadPc := backend.io.mem.loadPcRead
memBlock.io.ooo_to_mem.storePc := backend.io.mem.storePcRead
memBlock.io.ooo_to_mem.hybridPc := backend.io.mem.hyuPcRead
memBlock.io.ooo_to_mem.flushSb := backend.io.fenceio.sbuffer.flushSb
Expand Down
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