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area(csr): fix intr NO bits and remove reg for waddr/wdata #3970

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area(csr): fix intr NO bits and remove reg for waddr/wdata #3970

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sinceforYy
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@sinceforYy sinceforYy commented Dec 2, 2024 •
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  • Currently we support 61 major interrupts, and 8 bits are sufficient.

  • There is no need to use 64 bits to store the intermediate data of the interrupt NO.

  • In order to save area, we only need to add 1 cycle to wen, not waddr and wdata.

@sinceforYy sinceforYy force-pushed the fix-csr-reg branch 2 times, most recently from 3f2fc2e to e9e82d1 Compare December 2, 2024 10:26
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[Generated by IPC robot]
commit: e9e82d1

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
e9e82d1 1.959 0.450 2.687 1.230 2.832 2.461 2.393 0.919 1.407 1.992 3.434 2.709 2.383 3.261

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
2e5ebf5 1.959 0.450 2.686 1.238 2.832 2.461 2.393 0.919 1.407 1.992 3.435 2.709 2.383 3.261
908b24d
f0a1cc7 1.902 0.450 2.686 1.225 2.832 2.461 2.393 0.919 1.407 1.992 3.434 2.709 2.383 3.264
35850f1 1.902 0.450 2.686 1.222 2.832 2.461 2.393 0.919 1.407 1.992 3.434 2.709 2.383 3.264
dc4fac1 1.902 0.450 2.687 1.231 2.832 2.461 2.393 0.919 1.407 1.992 3.435 2.709 2.383 3.264

@sinceforYy sinceforYy changed the title area(csr): reduce CSR area area(csr): intr NO bits is reduced from 64 to 8 Dec 3, 2024
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[Generated by IPC robot]
commit: f67818e

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
f67818e 1.959 0.450 2.687 1.229 2.832 2.461 2.393 0.919 1.407 1.992 3.434 2.709 2.383 3.261

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
2e5ebf5 1.959 0.450 2.686 1.238 2.832 2.461 2.393 0.919 1.407 1.992 3.435 2.709 2.383 3.261
908b24d 1.902 0.450 2.686 1.223 2.832 2.461 2.393 0.919 1.407 1.992 3.434 2.709 2.383 3.264
f0a1cc7 1.902 0.450 2.686 1.225 2.832 2.461 2.393 0.919 1.407 1.992 3.434 2.709 2.383 3.264
35850f1 1.902 0.450 2.686 1.222 2.832 2.461 2.393 0.919 1.407 1.992 3.434 2.709 2.383 3.264
dc4fac1 1.902 0.450 2.687 1.231 2.832 2.461 2.393 0.919 1.407 1.992 3.435 2.709 2.383 3.264

@sinceforYy sinceforYy marked this pull request as ready for review December 5, 2024 03:32
@sinceforYy sinceforYy changed the title area(csr): intr NO bits is reduced from 64 to 8 area(csr): fix intr NO bits and remove 1 cycle for waddr/wdata Dec 9, 2024
@sinceforYy sinceforYy changed the title area(csr): fix intr NO bits and remove 1 cycle for waddr/wdata area(csr): fix intr NO bits and remove reg for waddr/wdata Dec 9, 2024
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[Generated by IPC robot]
commit: 321a9ec

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
321a9ec 1.959 0.450 2.687 1.225 2.832 2.461 2.393 0.919 1.407 1.992 3.434 2.709 2.383 3.261

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
fad7803
df65a16 1.959 0.450 2.686 1.238 2.832 2.461 2.393 0.919 1.407 1.992 3.434 2.709 2.383 3.261
7d20eb3 1.959 0.450 2.686 1.226 2.832 2.461 2.393 0.919 1.407 1.992 3.435 2.709 2.383 3.261
35477a7
493f6e1 1.959 0.450 2.686 1.224 2.832 2.461 2.393 0.919 1.407 1.992 3.435 2.709 2.383 3.261

Tang-Haojin
Tang-Haojin requested changes Dec 16, 2024
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src/main/scala/xiangshan/backend/fu/util/ClockGatedReg.scala Outdated
object GatedValidSignal {
def apply(next: Bool, init: Bool = false.B): Bool = {
val last = Wire(Bool())
last := RegEnable(next, init, next || last)
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Why we need this? Refer to OpenXiangShan/Utility#69.

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@sinceforYy sinceforYy force-pushed the fix-csr-reg branch 7 times, most recently from ba62685 to 0a2f86a Compare December 18, 2024 04:32
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[Generated by IPC robot]
commit: 0a2f86a

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
0a2f86a 1.952 0.439 2.696 1.228 2.847 2.457 2.366 0.933 1.400 1.979 3.418 2.726 2.383 3.272

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
a6696f0 1.952 0.439 2.696 1.228 2.847 2.457 2.366 0.933 1.400 1.979 3.418 2.726 2.383 3.272
c092d57 1.952 0.439 2.696 1.228 2.847 2.457 2.366 0.933 1.400 1.979 3.418 2.726 2.383 3.272
0ae34b3 1.952 0.439 2.696 1.228 2.847 2.457 2.366 0.933 1.400 1.979 3.418 2.726 2.383 3.272
042e89e 1.952 0.439 2.696 1.228 2.847 2.457 2.366 0.933 1.400 1.979 3.418 2.726 2.383 3.272
729ce9e 1.952 0.439 2.696 1.228 2.847 2.457 2.366 0.933 1.400 1.979 3.418 2.726 2.383 3.272

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@Tang-Haojin Tang-Haojin Tang-Haojin requested changes

@wissygh wissygh wissygh approved these changes

@huxuan0307 huxuan0307 huxuan0307 approved these changes

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@sinceforYy @XiangShanRobot @huxuan0307 @wissygh @Tang-Haojin