fix(csr, gate): add valid signal gate in csr

src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala

@@ -13,7 +13,7 @@ import xiangshan.backend.fu.NewCSR.CSRDefines._
 import xiangshan.backend.fu.NewCSR.CSREnumTypeImplicitCast._
 import xiangshan.backend.fu.NewCSR.CSREvents.{CSREvents, DretEventSinkBundle, EventUpdatePrivStateOutput, MNretEventSinkBundle, MretEventSinkBundle, SretEventSinkBundle, TargetPCBundle, TrapEntryDEventSinkBundle, TrapEntryEventInput, TrapEntryHSEventSinkBundle, TrapEntryMEventSinkBundle, TrapEntryMNEventSinkBundle, TrapEntryVSEventSinkBundle}
 import xiangshan.backend.fu.fpu.Bundles.Frm
-import xiangshan.backend.fu.util.CSRConst
+import xiangshan.backend.fu.util._
 import xiangshan.backend.fu.vector.Bundles.{Vl, Vstart, Vxrm, Vxsat}
 import xiangshan.backend.fu.wrapper.CSRToDecode
 import xiangshan.backend.rob.RobPtr
@@ -292,7 +292,7 @@ class NewCSR(implicit val p: Parameters) extends Module
   val legalMNret = permitMod.io.out.hasLegalMNret
   val legalDret  = permitMod.io.out.hasLegalDret
 
-  private val wenLegalReg = GatedValidRegNext(wenLegal)
+  private val wenLegalReg = GatedValidSignal(wenLegal)
 
   var csrRwMap: SeqMap[Int, (CSRAddrWriteBundle[_], UInt)] =
     machineLevelCSRMap ++
@@ -544,8 +544,8 @@ class NewCSR(implicit val p: Parameters) extends Module
         // Todo: move RegNext from ROB to CSR
         m.robCommit.instNum := io.fromRob.commit.instNum
         m.robCommit.fflags  := RegNextWithEnable(io.fromRob.commit.fflags)
-        m.robCommit.fsDirty := GatedValidRegNext(io.fromRob.commit.fsDirty)
-        m.robCommit.vsDirty := GatedValidRegNext(io.fromRob.commit.vsDirty)
+        m.robCommit.fsDirty := GatedValidSignal(io.fromRob.commit.fsDirty)
+        m.robCommit.vsDirty := GatedValidSignal(io.fromRob.commit.vsDirty)
         m.robCommit.vxsat   := RegNextWithEnable(io.fromRob.commit.vxsat)
         m.robCommit.vtype   := RegNextWithEnable(io.fromRob.commit.vtype)
         m.robCommit.vl      := RegNext          (io.fromRob.commit.vl)
@@ -1258,9 +1258,9 @@ class NewCSR(implicit val p: Parameters) extends Module
   toAIA.vsClaim := vstopei.w.wen
 
   // tlb
-  io.tlb.satpASIDChanged  := GatedValidRegNext(satp.w.wen  && satp .regOut.ASID =/=  satp.w.wdataFields.ASID)
-  io.tlb.vsatpASIDChanged := GatedValidRegNext(vsatp.w.wen && vsatp.regOut.ASID =/= vsatp.w.wdataFields.ASID)
-  io.tlb.hgatpVMIDChanged := GatedValidRegNext(hgatp.w.wen && hgatp.regOut.VMID =/= hgatp.w.wdataFields.VMID)
+  io.tlb.satpASIDChanged  := GatedValidSignal(satp.w.wen  && satp .regOut.ASID =/=  satp.w.wdataFields.ASID)
+  io.tlb.vsatpASIDChanged := GatedValidSignal(vsatp.w.wen && vsatp.regOut.ASID =/= vsatp.w.wdataFields.ASID)
+  io.tlb.hgatpVMIDChanged := GatedValidSignal(hgatp.w.wen && hgatp.regOut.VMID =/= hgatp.w.wdataFields.VMID)
   io.tlb.satp := satp.rdata
   io.tlb.vsatp := vsatp.rdata
   io.tlb.hgatp := hgatp.rdata

src/main/scala/xiangshan/backend/fu/util/ClockGatedReg.scala

@@ -0,0 +1,13 @@
+package xiangshan.backend.fu.util
+
+import chisel3._
+import chisel3.util._
+
+
+object GatedValidSignal {
+  def apply(next: Bool): Bool = {
+    val last = Wire(Bool())
+    last := RegEnable(next, next || last)
+    last
+  }
+}