submodule: bump submodule yunsuan, rocket-chip, and ready-to-run #4040
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… ready-to-run
Bump spike ref in ready-to-run
* spike commit: c7d70452b8aa90631393314f4ad7a0c6f60fd987
* spike config: CPU=XIANGSHAN
Including:
* feat(difftest): sync FS/VS dirty from DUT to REF.
* feat(rvv): Align XS on whether vector instructions set VS dirty.
Bump nemu ref in ready-to-run
* NEMU commit: cc72c9aa97dc2504f807191d03c57242da5aaeda
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
Including:
* fix(vector): always set vs.dirty when inst may change vector state (OpenXiangShan#716)
* fix(zvfh): fix sew check for vfmvsf and vfmvfs (OpenXiangShan#717)
* fix(is_ctrl): set is_ctrl is true when get rtl_priv_jr exec (OpenXiangShan#718)
* fix(vector): checking frm before execute for vector float instructions (OpenXiangShan#719)
* feat(difftest): sync FS/VS dirty from DUT(NEMU) to REF(Spike).
* submodule(ready-to-run): Bump spike ref in ready-to-run
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[Generated by IPC robot]
master branch:
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Bump spike ref in ready-to-run
Including:
* feat(difftest): sync FS/VS dirty from DUT to REF.
* feat(rvv): Align XS on whether vector instructions set VS dirty.
Bump nemu ref in ready-to-run
Including:
* fix(vector): always set vs.dirty when inst may change vector state (#716)
* fix(zvfh): fix sew check for vfmvsf and vfmvfs (#717)
* fix(is_ctrl): set is_ctrl is true when get rtl_priv_jr exec (#718)
* fix(vector): checking frm before execute for vector float instructions (#719)
* feat(difftest): sync FS/VS dirty from DUT(NEMU) to REF(Spike).
* submodule(ready-to-run): Bump spike ref in ready-to-run