feat: compile-time logging

[eastonman]

I propose standardising compile-time logging using scala-logging instead of println.

The main purpose of using a logging framework is to switch compile-time logging levels easily. At present (2024-12-10), XiangShan prints very detailed STDOUT when compiling, including issueQueue connection details, wakeUp network details and even every CSR. These information is not useful when working on other modules. In contrast, useful debug info is buried in huge amount of STDOUT print.
Therefore I propose using scala-logging as a logging framework, and the following definition mapping for log-level.

• trace: very detailed source-sink info, struct member info, etc.
• debug: useful params for debugging. e.g., regCache ports, arbitrary priority, etc.
• info: params that an end user may want to know. e.g., cache size, tlb size, queue sizes, fu amount, etc.
• warn: something that should raise the attention of the end user, but still can compile. e.g., sub-optimal custom config, SRAM too small, high latency combinational logic, etc.
• error: the params provided by the end user are insane, and the compile process cannot continue.

The example output of default logging level INFO is as follows. Note that this is incomplete and more work is going on to transform println to logger.xxx.

[724] 2024-12-10 13:30:50 INFO  x.f.icache.ICacheImp     | ICache:
[724] 2024-12-10 13:30:50 INFO  x.f.icache.ICacheImp     |   TagECC: Some(parity)
[724] 2024-12-10 13:30:50 INFO  x.f.icache.ICacheImp     |   DataECC: Some(parity)
[724] 2024-12-10 13:30:50 INFO  x.f.icache.ICacheImp     |   ICacheSets: 256
[724] 2024-12-10 13:30:50 INFO  x.f.icache.ICacheImp     |   ICacheWays: 4
[724] 2024-12-10 13:30:50 INFO  x.f.icache.ICacheImp     |   PortNumber: 2
[724] 2024-12-10 13:30:50 INFO  x.f.icache.ICacheImp     |   nFetchMshr: 4
[724] 2024-12-10 13:30:50 INFO  x.f.icache.ICacheImp     |   nPrefetchMshr: 10
[724] 2024-12-10 13:30:50 INFO  x.f.icache.ICacheImp     |   nWayLookupSize: 32
[724] 2024-12-10 13:30:50 INFO  x.f.icache.ICacheImp     |   DataCodeUnit: 64
[724] 2024-12-10 13:30:50 INFO  x.f.icache.ICacheImp     |   ICacheDataBanks: 8
[724] 2024-12-10 13:30:50 INFO  x.f.icache.ICacheImp     |   ICacheDataSRAMWidth: 66
[724] 2024-12-10 13:30:53 INFO  x.frontend.Composer      | bypassing output of fast pred: FauFTB
[724] 2024-12-10 13:30:53 INFO  x.frontend.Composer      | total meta size: 409
[724] 2024-12-10 13:30:53 INFO  x.frontend.Predictor     | history buffer length 256
[724] 2024-12-10 13:30:56 INFO  xiangshan.frontend.Ftq   | ftq redirect MEM: 64 x 86
[724] 2024-12-10 13:31:01 INFO  xiangshan.cache.mmu.TLB  | itlb:
[724] 2024-12-10 13:31:01 INFO  xiangshan.cache.mmu.TLB  |   entries: 48
[724] 2024-12-10 13:31:01 INFO  xiangshan.cache.mmu.TLB  |   associative: fa
[724] 2024-12-10 13:31:01 INFO  xiangshan.cache.mmu.TLB  |   replacer: plru
[724] 2024-12-10 13:31:07 INFO  x.backend.rename.Rename  | numRegSrc: 5
[724] 2024-12-10 13:31:14 INFO  x.b.i.SchedulerArithImp  | numWriteRegCache: 4
[724] 2024-12-10 13:31:23 INFO  x.b.i.SchedulerMemImp    | numWriteRegCache: 3
[724] 2024-12-10 13:31:23 INFO  x.b.i.SchedulerMemImp    | memAddrIQs.size: 7, enq.size: 7
[724] 2024-12-10 13:31:23 INFO  x.b.i.SchedulerMemImp    | stAddrIQs.size:  2, enq.size: 2
[724] 2024-12-10 13:31:23 INFO  x.b.i.SchedulerMemImp    | ldAddrIQs.size:  3, enq.size: 3
[724] 2024-12-10 13:31:23 INFO  x.b.i.SchedulerMemImp    | stDataIQs.size:  2, enq.size: 2
[724] 2024-12-10 13:31:23 INFO  x.b.i.SchedulerMemImp    | hyuIQs.size:     0, enq.size: 0
[724] 2024-12-10 13:31:25 INFO  x.b.fu.NewCSR.NewCSR     | [CSR] supported isa ext: ABCDFHIMSUV
[724] 2024-12-10 13:31:27 INFO  x.b.f.N.CommitIDModule   | commit SHA=e24c12b749
[724] 2024-12-10 13:31:27 INFO  x.b.f.N.CommitIDModule   | dirty=true

Currently, switching the log-level is done by make VERBOSE=1 which sets the log-level to ALL. Maybe more options should be added to control every level of logging.