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feat: compile-time logging #4015

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6 changes: 6 additions & 0 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -112,6 +112,12 @@ ifeq ($(WITH_CONSTANTIN),1)
override SIM_ARGS += --with-constantin
endif

# verbose compile-time logging
ifeq ($(VERBOSE),1)
RELEASE_ARGS += --verbose
DEBUG_ARGS += --verbose
endif

# emu for the release version
RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem
DEBUG_ARGS += --enable-difftest
Expand Down
17 changes: 13 additions & 4 deletions build.sc
Original file line number Diff line number Diff line change
Expand Up @@ -63,6 +63,14 @@ trait HasChisel extends SbtModule {
override def scalacPluginIvyDeps = super.scalacPluginIvyDeps() ++ Agg(chiselPluginIvy.get)
}

trait HasLogging extends SbtModule {
override def ivyDeps: T[Agg[Dep]] = super.ivyDeps() ++ Agg(
ivy"com.typesafe.scala-logging::scala-logging:3.9.5",
ivy"ch.qos.logback:logback-classic:1.5.12",
ivy"org.fusesource.jansi:jansi:1.17",
)
}

object rocketchip
extends $file.`rocket-chip`.common.RocketChipModule
with HasChisel {
Expand Down Expand Up @@ -109,7 +117,7 @@ object rocketchip
}
}

object utility extends HasChisel {
object utility extends HasChisel with HasLogging {

override def millSourcePath = pwd / "utility"

Expand Down Expand Up @@ -233,7 +241,7 @@ trait XiangShanModule extends ScalaModule {
override def forkEnv = Map("PATH" -> envPATH)
}

object xiangshan extends XiangShanModule with HasChisel with ScalafmtModule {
object xiangshan extends XiangShanModule with HasChisel with HasLogging with ScalafmtModule {

override def millSourcePath = pwd

Expand All @@ -255,7 +263,7 @@ object xiangshan extends XiangShanModule with HasChisel with ScalafmtModule {

def macrosModule = macros

override def forkArgs = Seq("-Xmx40G", "-Xss256m")
override def forkArgs = Seq("-Xmx40G", "-Xss256m", "-Dlogback.configurationFile=src/main/resources/logback.xml")

override def ivyDeps = super.ivyDeps() ++ Agg(
defaultVersions("chiseltest"),
Expand Down Expand Up @@ -326,7 +334,8 @@ object xiangshan extends XiangShanModule with HasChisel with ScalafmtModule {
}

object test extends SbtTests with TestModule.ScalaTest {
override def forkArgs = Seq("-Xmx40G", "-Xss256m")
override def forkArgs = Seq("-Xmx40G", "-Xss256m",
"-Dlogback.configurationFile=src/main/resources/logback.xml", "-XX:+UseShenandoahGC")

override def ivyDeps = super.ivyDeps() ++ Agg(
defaultVersions("chiseltest")
Expand Down
10 changes: 10 additions & 0 deletions src/main/resources/logback.xml
Original file line number Diff line number Diff line change
@@ -0,0 +1,10 @@
<configuration>
<appender name="STDOUT" class="ch.qos.logback.core.ConsoleAppender">
<encoder>
<pattern>%gray(%d{yyyy-MM-dd HH:mm:ss}) %highlight(%-5level) %cyan(%-24logger{24}) | %msg%n</pattern>
</encoder>
</appender>
<root level="${LOG_LEVEL:-INFO}">
<appender-ref ref="STDOUT" />
</root>
</configuration>
3 changes: 3 additions & 0 deletions src/main/scala/top/ArgParser.scala
Original file line number Diff line number Diff line change
Expand Up @@ -146,6 +146,9 @@ object ArgParser {
case "--firtool-opt" :: option :: tail =>
firtoolOpts ++= option.split(" ").filter(_.nonEmpty)
nextOption(config, tail)
case "--verbose" :: tail =>
System.setProperty("LOG_LEVEL", "all")
nextOption(config, tail)
case option :: tail =>
// unknown option, maybe a firrtl option, skip
firrtlOpts :+= option
Expand Down
3 changes: 2 additions & 1 deletion src/main/scala/xiangshan/Parameters.scala
Original file line number Diff line number Diff line change
Expand Up @@ -46,6 +46,7 @@ import coupledL2._
import coupledL2.tl2chi._
import xiangshan.backend.datapath.WakeUpConfig
import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams}
import com.typesafe.scalalogging.LazyLogging

import scala.math.{max, min, pow}

Expand Down Expand Up @@ -580,7 +581,7 @@ case class DebugOptions
EnableRollingDB: Boolean = false
)

trait HasXSParameter {
trait HasXSParameter extends LazyLogging {

implicit val p: Parameters

Expand Down
62 changes: 31 additions & 31 deletions src/main/scala/xiangshan/backend/Backend.scala
Original file line number Diff line number Diff line change
Expand Up @@ -83,7 +83,7 @@ class BackendInlined(val params: BackendParams)(implicit p: Parameters) extends
ibp.updateIdx(idx)
}

println(params.iqWakeUpParams)
logger.debug(s"${params.iqWakeUpParams}")

for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) {
schdCfg.bindBackendParam(params)
Expand All @@ -99,14 +99,14 @@ class BackendInlined(val params: BackendParams)(implicit p: Parameters) extends
exuCfg.updateExuIdx(i)
}

println("[Backend] ExuConfigs:")
logger.debug("ExuConfigs:")
for (exuCfg <- params.allExuParams) {
val fuConfigs = exuCfg.fuConfigs
val wbPortConfigs = exuCfg.wbPortConfigs
val immType = exuCfg.immType

println("[Backend] " +
s"${exuCfg.name}: " +
logger.debug(
s" ${exuCfg.name}: " +
(if (exuCfg.fakeUnit) "fake, " else "") +
(if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") +
s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " +
Expand All @@ -132,47 +132,47 @@ class BackendInlined(val params: BackendParams)(implicit p: Parameters) extends
)
}

println(s"[Backend] all fu configs")
logger.trace(s"all fu configs")
for (cfg <- FuConfig.allConfigs) {
println(s"[Backend] $cfg")
logger.trace(s" $cfg")
}

println(s"[Backend] Int RdConfigs: ExuName(Priority)")
logger.trace(s"Int RdConfigs: ExuName(Priority)")
for ((port, seq) <- params.getRdPortParams(IntData())) {
println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
logger.trace(s" port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
}

println(s"[Backend] Int WbConfigs: ExuName(Priority)")
logger.trace(s"Int WbConfigs: ExuName(Priority)")
for ((port, seq) <- params.getWbPortParams(IntData())) {
println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
logger.trace(s" port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
}

println(s"[Backend] Fp RdConfigs: ExuName(Priority)")
logger.trace(s"Fp RdConfigs: ExuName(Priority)")
for ((port, seq) <- params.getRdPortParams(FpData())) {
println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
logger.trace(s" port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
}

println(s"[Backend] Fp WbConfigs: ExuName(Priority)")
logger.trace(s"Fp WbConfigs: ExuName(Priority)")
for ((port, seq) <- params.getWbPortParams(FpData())) {
println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
logger.trace(s" port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
}

println(s"[Backend] Vf RdConfigs: ExuName(Priority)")
logger.trace(s"Vf RdConfigs: ExuName(Priority)")
for ((port, seq) <- params.getRdPortParams(VecData())) {
println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
logger.trace(s" port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
}

println(s"[Backend] Vf WbConfigs: ExuName(Priority)")
logger.trace(s"Vf WbConfigs: ExuName(Priority)")
for ((port, seq) <- params.getWbPortParams(VecData())) {
println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
logger.trace(s" port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}")
}

println(s"[Backend] Dispatch Configs:")
println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})")
println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})")
logger.info(s"Dispatch Configs:")
logger.info(s" Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})")
logger.info(s" Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})")

params.updateCopyPdestInfo
println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}")
logger.trace(s"copyPdestInfo ${params.copyPdestInfo}")
params.allExuParams.map(_.copyNum)
val ctrlBlock = LazyModule(new CtrlBlock(params))
val pcTargetMem = LazyModule(new PcTargetMem(params))
Expand Down Expand Up @@ -220,7 +220,7 @@ class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parame
memScheduler.io.toSchedulers.wakeupVec
).map(x => (x.bits.exuIdx, x)).toMap

println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}")
logger.trace(s"iq wake up keys: ${iqWakeUpMappedBundle.keys}")

wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable
wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable
Expand Down Expand Up @@ -376,8 +376,8 @@ class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parame

dataPath.io.ldCancel := io.mem.ldCancel

println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}")
println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}")
logger.trace(s"wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}")
logger.trace(s"wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}")
dataPath.io.fromIntWb := wbDataPath.io.toIntPreg
dataPath.io.fromFpWb := wbDataPath.io.toFpPreg
dataPath.io.fromVfWb := wbDataPath.io.toVfPreg
Expand All @@ -401,9 +401,9 @@ class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parame
}
og2ForVector.io.fromOg1ImmInfo := dataPath.io.og1ImmInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1)

println(s"[Backend] BypassNetwork OG1 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filterNot(_._2.needOg2Resp).size}")
println(s"[Backend] BypassNetwork OG2 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).size}")
println(s"[Backend] bypassNetwork.io.fromDataPath.mem: ${bypassNetwork.io.fromDataPath.mem.size}, dataPath.io.toMemExu: ${dataPath.io.toMemExu.size}")
logger.trace(s"BypassNetwork OG1 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filterNot(_._2.needOg2Resp).size}")
logger.trace(s"BypassNetwork OG2 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).size}")
logger.trace(s"bypassNetwork.io.fromDataPath.mem: ${bypassNetwork.io.fromDataPath.mem.size}, dataPath.io.toMemExu: ${dataPath.io.toMemExu.size}")
bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu
bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu
bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfArithExu
Expand Down Expand Up @@ -598,8 +598,8 @@ class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parame
private val memIssueParams = params.memSchdParams.get.issueBlockParams
private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu))
private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu))
println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU")
println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad")
logger.debug(s"memExuBlocksHasLDU: $memExuBlocksHasLDU")
logger.debug(s"memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad")

private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType)
for (i <- toMem.indices) {
Expand Down Expand Up @@ -812,7 +812,7 @@ class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parame

if (printEventCoding) {
for (((name, inc), i) <- allPerfEvents.zipWithIndex) {
println("backend perfEvents Set", name, inc, i)
logger.trace(f"Backend perfEvents Set, ${name}, ${inc}, ${i}")
}
}

Expand Down
13 changes: 7 additions & 6 deletions src/main/scala/xiangshan/backend/BackendParams.scala
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,7 @@ package xiangshan.backend
import org.chipsalliance.cde.config.Parameters
import chisel3._
import chisel3.util._
import com.typesafe.scalalogging.LazyLogging
import xiangshan.backend.Bundles._
import xiangshan.backend.datapath.DataConfig._
import xiangshan.backend.datapath.RdConfig._
Expand All @@ -36,7 +37,7 @@ case class BackendParams(
schdParams : Map[SchedulerType, SchdBlockParams],
pregParams : Seq[PregParams],
iqWakeUpParams : Seq[WakeUpConfig],
) {
) extends LazyLogging {

def debugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).EnableDifftest

Expand All @@ -51,13 +52,13 @@ case class BackendParams(
copyPdestInfo.contains(exuIdx)
}
def connectWakeup(exuIdx: Int): Unit = {
println(s"[Backend] copyPdestInfo ${copyPdestInfo}")
logger.trace(s"[Backend] copyPdestInfo ${copyPdestInfo}")
if (copyPdestInfo.contains(exuIdx)) {
println(s"[Backend] exuIdx ${exuIdx} be connected, old info ${copyPdestInfo(exuIdx)}")
logger.trace(s"[Backend] exuIdx ${exuIdx} be connected, old info ${copyPdestInfo(exuIdx)}")
val newInfo = exuIdx -> (copyPdestInfo(exuIdx)._1, copyPdestInfo(exuIdx)._2 + 1)
copyPdestInfo.remove(exuIdx)
copyPdestInfo += newInfo
println(s"[Backend] exuIdx ${exuIdx} be connected, new info ${copyPdestInfo(exuIdx)}")
logger.trace(s"[Backend] exuIdx ${exuIdx} be connected, new info ${copyPdestInfo(exuIdx)}")
}
}
def getCopyPdestIndex(exuIdx: Int): Int = {
Expand Down Expand Up @@ -436,7 +437,7 @@ case class BackendParams(
val rdTypes = Seq(IntRD(), FpRD(), VfRD())
for(wbType <- wbTypes){
for(rdType <- rdTypes){
println(s"[BackendParams] wbType: ${wbType}, rdType: ${rdType}")
logger.trace(s"[BackendParams] wbType: ${wbType}, rdType: ${rdType}")
allRealExuParams.map {
case exuParam =>
val wbPortConfigs = exuParam.wbPortConfigs
Expand All @@ -458,7 +459,7 @@ case class BackendParams(
.sortBy(_._1.get.priority)
.groupBy(_._1.get.port).map { case (wbPort, intWbRdPairs) =>
val rdCfgs = intWbRdPairs.map(_._2).flatten
println(s"[BackendParams] wb port ${wbPort} rdcfgs: ${rdCfgs}")
logger.trace(s"[BackendParams] wb port ${wbPort} rdcfgs: ${rdCfgs}")
rdCfgs.groupBy(_.port).foreach { case (p, rdCfg) =>
//println(s"[BackendParams] rdport: ${p}, cfgs: ${rdCfg}")
rdCfg.zip(rdCfg.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority, s"an exu has high priority at ${wbType} wb port ${wbPort}, but has low priority at ${rdType} rd port ${p}") }
Expand Down
2 changes: 1 addition & 1 deletion src/main/scala/xiangshan/backend/MemBlock.scala
Original file line number Diff line number Diff line change
Expand Up @@ -1924,7 +1924,7 @@ class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer)

if (printEventCoding) {
for (((name, inc), i) <- allPerfEvents.zipWithIndex) {
println("MemBlock perfEvents Set", name, inc, i)
logger.trace("MemBlock perfEvents Set", name, inc, i)
}
}

Expand Down
16 changes: 8 additions & 8 deletions src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,7 @@ class BypassNetwork()(implicit p: Parameters, params: BackendParams) extends XSM
private val fromDPsRCData: Seq[Vec[UInt]] = io.fromDataPath.rcData.flatten.toSeq
private val immInfo = io.fromDataPath.immInfo

println(s"[BypassNetwork] RCData num: ${fromDPsRCData.size}")
logger.debug(s"[BypassNetwork] RCData num: ${fromDPsRCData.size}")

// (exuIdx, srcIdx, bypassExuIdx)
private val forwardOrBypassValidVec3: MixedVec[Vec[Vec[Bool]]] = MixedVecInit(
Expand All @@ -92,7 +92,7 @@ class BypassNetwork()(implicit p: Parameters, params: BackendParams) extends XSM
}
m := vecMask
}
println(s"[BypassNetwork] ${x.bits.params.name} numRegSrc: ${x.bits.params.numRegSrc}")
logger.trace(s"[BypassNetwork] ${x.bits.params.name} numRegSrc: ${x.bits.params.numRegSrc}")
VecInit(x.bits.l1ExuOH.getOrElse(
// TODO: remove tmp max 1 for fake HYU1
VecInit(Seq.fill(x.bits.params.numRegSrc max 1)(VecInit(0.U(ExuVec.width.W).asBools)))
Expand All @@ -115,7 +115,7 @@ class BypassNetwork()(implicit p: Parameters, params: BackendParams) extends XSM
private val vfExuNum = params.vfSchdParams.get.numExu
private val memExuNum = params.memSchdParams.get.numExu

println(s"[BypassNetwork] allExuNum: ${toExus.size} intExuNum: ${intExuNum} fpExuNum: ${fpExuNum} vfExuNum: ${vfExuNum} memExuNum: ${memExuNum}")
logger.trace(s"[BypassNetwork] allExuNum: ${toExus.size} intExuNum: ${intExuNum} fpExuNum: ${fpExuNum} vfExuNum: ${vfExuNum} memExuNum: ${memExuNum}")

private val fromDPsHasBypass2Source = fromDPs.filter(x => x.bits.params.isIQWakeUpSource && x.bits.params.writeVfRf && (x.bits.params.isVfExeUnit || x.bits.params.hasLoadExu)).map(_.bits.params.exuIdx)
private val fromDPsHasBypass2Sink = fromDPs.filter(x => x.bits.params.isIQWakeUpSink && x.bits.params.readVfRf && (x.bits.params.isVfExeUnit || x.bits.params.isMemExeUnit)).map(_.bits.params.exuIdx)
Expand All @@ -135,9 +135,9 @@ class BypassNetwork()(implicit p: Parameters, params: BackendParams) extends XSM
fromDPsHasBypass2Source.map(x => RegEnable(bypassDataVec(x), bypass2DateEn(x).asBool))
)

println(s"[BypassNetwork] HasBypass2SourceExuNum: ${fromDPsHasBypass2Source.size} HasBypass2SinkExuNum: ${fromDPsHasBypass2Sink.size} bypass2DataVecSize: ${bypass2DataVec.length}")
println(s"[BypassNetwork] HasBypass2SourceExu: ${fromDPsHasBypass2Source}")
println(s"[BypassNetwork] HasBypass2SinkExu: ${fromDPsHasBypass2Sink}")
logger.trace(s"[BypassNetwork] HasBypass2SourceExuNum: ${fromDPsHasBypass2Source.size} HasBypass2SinkExuNum: ${fromDPsHasBypass2Sink.size} bypass2DataVecSize: ${bypass2DataVec.length}")
logger.trace(s"[BypassNetwork] HasBypass2SourceExu: ${fromDPsHasBypass2Source}")
logger.trace(s"[BypassNetwork] HasBypass2SinkExu: ${fromDPsHasBypass2Sink}")

toExus.zip(fromDPs).foreach { case (sink, source) =>
sink <> source
Expand Down Expand Up @@ -165,7 +165,7 @@ class BypassNetwork()(implicit p: Parameters, params: BackendParams) extends XSM
val readRegCache = if (exuParm.needReadRegCache) exuInput.bits.dataSources(srcIdx).readRegCache else false.B
val readImm = if (exuParm.immType.nonEmpty || exuParm.hasLoadExu) exuInput.bits.dataSources(srcIdx).readImm else false.B
val bypass2ExuIdx = fromDPsHasBypass2Sink.indexOf(exuIdx)
println(s"${exuParm.name}: bypass2ExuIdx is ${bypass2ExuIdx}")
logger.trace(s"${exuParm.name}: bypass2ExuIdx is ${bypass2ExuIdx}")
val readBypass2 = if (bypass2ExuIdx >= 0) dataSource.readBypass2 else false.B
src := Mux1H(
Seq(
Expand Down Expand Up @@ -200,7 +200,7 @@ class BypassNetwork()(implicit p: Parameters, params: BackendParams) extends XSM
fromExus.zip(bypassDataVec).filter(_._1.bits.params.needWriteRegCache).map(_._2)
)

println(s"[BypassNetwork] WriteRegCacheExuNum: ${forwardIntWenVec.size}")
logger.debug(s"[BypassNetwork] WriteRegCacheExuNum: ${forwardIntWenVec.size}")

io.toDataPath.zipWithIndex.foreach{ case (x, i) =>
x.wen := bypassIntWenVec(i)
Expand Down
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