CVM Development #3980
CVM Development #3980
Conversation
yxtx1994
commented
Dec 4, 2024
yxtx1994
commented
- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI protoco
- We can don't using these modules by setting the option HasCVMExtension&HasMEMencryption to false
…|| ishptw) [fix] the signal “toLLPTW” gen logic(s2xlate === noS2xlate || s2xlate === onlyStage1) [fix] the handle flow of jmp_bitmap_check and s2xlate === onlyStage2 request in PTW
[feat] Add the option to implement the Memenc module in CVMconfig
…ption module [feat] delete unnecessary parameters in Soc
…ryptCSR is default ture.
[feat] Add lock logic for CSR MCVM.BME&BMA when BME is valid.
…x from ParallelMux.
[feat] Add BCLARE bit in CSR MCVM used for clear bitmap cache [fix] bitmap req merge logic of enq entry and after lookup cache entry [feat] remove bitmapReg clear logic in PTWCache for *fence, add clear logic when refill l0&sp [fix] latch and update more state when PTW get jmp_bitmap_check req
[fix] l0BitmapReg wakeup uses pte_index without OHToUInt [fix] bmppn compare and need_addr_check logic in LLPTW
yxtx1994
requested review from
good-circle,
cebarobot,
Lemover and
eastonman
as code owners
| * See the Mulan PSL v2 for more details. | ||
| ***************************************************************************************/ | ||
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| // See LICENSE.SiFive for license details. |
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What's this? Is this code derived from rocket-chip?
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This code dose not derived from rocket-chip, just import some packages of rocket-chip.
I didn't know if I should add a license for this, so I left it for now.
If it is not needed, I will delete it.
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import package does not need to add a license
| * See the Mulan PSL v2 for more details. | ||
| ***************************************************************************************/ | ||
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| // See LICENSE.SiFive for license details. |
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Same response as the last conversation.
| val res_pmp = pmp_match_res(leaveHitMux, io.req.valid)(req.addr(PMPAddrBits-PMPKeyIDBits-1, 0), req.size, io.check_env.pmp, io.check_env.mode, lgMaxSize) | ||
| val res_pma = pma_match_res(leaveHitMux, io.req.valid)(req.addr(PMPAddrBits-PMPKeyIDBits-1, 0), req.size, io.check_env.pma, io.check_env.mode, lgMaxSize) |
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Is this behaviour correct when CVM is disabled?
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When "HasCVMExtension = Some(true)", the actual physical address bit width change to "PAddrBits-KeyIDBits".
In this config, if CVM is disabled, the KeyID must be "0" and PMP/PMA only need to check actual physical address bit.
When "HasCVMExtension = Some(false)", KeyIDBits should be set to "0"(I will fix it in file SoC.scals).
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I suggest adding some comments about what a KeyID is and what it does under the abovementioned circumstances.
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I agree with your suggestion and I will add relevant comments in the next commit.
