CVM Development

src/main/scala/system/SoC.scala

@@ -19,7 +19,7 @@ package system
 import org.chipsalliance.cde.config.{Field, Parameters}
 import chisel3._
 import chisel3.util._
-import device.{DebugModule, TLPMA, TLPMAIO}
+import device.{DebugModule, TLPMA, TLPMAIO, AXI4MemEncrypt}
 import freechips.rocketchip.amba.axi4._
 import freechips.rocketchip.devices.debug.DebugModuleKey
 import freechips.rocketchip.devices.tilelink._
@@ -50,6 +50,11 @@ case class SoCParameters
   PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1),
   PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff),
   UARTLiteForDTS: Boolean = true, // should be false in SimMMIO
+  MEMENCRange: AddressSet = AddressSet(0x38030000L, 0xfff),
+  KeyIDBits: Int = 5,
+  MemencPipes: Int = 4,
+  HasMEMencryption: Option[Boolean] = Some(false),
+  HasDelayNoencryption: Option[Boolean] = Some(false), // Test specific
   extIntrs: Int = 64,
   L3NBanks: Int = 4,
   L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
@@ -115,6 +120,8 @@ trait HasSoCParameter {
   val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined)
     soc.EnableCHIAsyncBridge else None
   val EnableClintAsyncBridge = soc.EnableClintAsyncBridge
+
+  def HasMEMencryption = soc.HasMEMencryption.getOrElse(false)
 }
 
 trait HasPeripheralRanges {
@@ -132,6 +139,7 @@ trait HasPeripheralRanges {
     "PLIC"  -> soc.PLICRange,
     "PLL"   -> soc.PLLRange,
     "UART"  -> soc.UARTLiteRange,
+    "MEMENC"  -> soc.MEMENCRange,
     "DEBUG" -> dm.get.address,
     "MMPMA" -> AddressSet(mmpma.address, mmpma.mask)
   ) ++ (
@@ -249,15 +257,30 @@ trait HaveAXI4MemPort {
       TLBuffer.chainNode(2) :=
       mem_xbar
   }
+  val axi4memencrpty = if(HasMEMencryption) Some(LazyModule(new AXI4MemEncrypt(soc.MEMENCRange))) else None
+  if(HasMEMencryption){
+    memAXI4SlaveNode :=
+      AXI4Buffer() :=
+      AXI4Buffer() :=
+      AXI4Buffer() :=
+      AXI4IdIndexer(idBits = 14) :=
+      AXI4UserYanker() :=
+      axi4memencrpty.get.node
+
+    axi4memencrpty.get.node :=
+      AXI4Deinterleaver(L3BlockSize) :=
+      axi4mem_node
+  }else{
+    memAXI4SlaveNode :=
+      AXI4Buffer() :=
+      AXI4Buffer() :=
+      AXI4Buffer() :=
+      AXI4IdIndexer(idBits = 14) :=
+      AXI4UserYanker() :=
+      AXI4Deinterleaver(L3BlockSize) :=
+      axi4mem_node
+  }
 
-  memAXI4SlaveNode :=
-    AXI4Buffer() :=
-    AXI4Buffer() :=
-    AXI4Buffer() :=
-    AXI4IdIndexer(idBits = 14) :=
-    AXI4UserYanker() :=
-    AXI4Deinterleaver(L3BlockSize) :=
-    axi4mem_node
 
   val memory = InModuleBody {
     memAXI4SlaveNode.makeIOs()
@@ -421,8 +444,14 @@ class MemMisc()(implicit p: Parameters) extends BaseSoC
   val pma = LazyModule(new TLPMA)
   if (enableCHI) {
     pma.node := TLBuffer.chainNode(4) := device_xbar.get
+    if(HasMEMencryption){
+      axi4memencrpty.get.ctrl_node := TLToAPB() := device_xbar.get
+    }
   } else {
     pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
+    if(HasMEMencryption){
+      axi4memencrpty.get.ctrl_node := TLToAPB() := peripheralXbar.get
+    }
   }
 
   class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
@@ -447,6 +476,11 @@ class MemMisc()(implicit p: Parameters) extends BaseSoC
 
     pma.module.io <> cacheable_check
 
+    if(HasMEMencryption){
+      val cnt = Counter(true.B, 8)._1
+      axi4memencrpty.get.module.io.random_val := axi4memencrpty.get.module.io.random_req && cnt(2).asBool
+      axi4memencrpty.get.module.io.random_data := cnt(0).asBool
+    }
     // positive edge sampling of the lower-speed rtc_clock
     val rtcTick = RegInit(0.U(3.W))
     rtcTick := Cat(rtcTick(1, 0), rtc_clock)

src/main/scala/top/Configs.scala

@@ -384,6 +384,26 @@ class WithFuzzer extends Config((site, here, up) => {
   }
 })
 
+class CVMCompile extends Config((site, here, up) => {
+  case SoCParamsKey => up(SoCParamsKey).copy(
+    HasMEMencryption = Some(true),
+    HasDelayNoencryption = Some(false)
+  )
+  case XSTileKey => up(XSTileKey).map(_.copy(
+    HasCVMExtension = Some(true),
+    HasBitmapCheckDefault = Some(false)))
+})
+
+class CVMTestCompile extends Config((site, here, up) => {
+  case SoCParamsKey => up(SoCParamsKey).copy(
+    HasMEMencryption = Some(true),
+    HasDelayNoencryption = Some(true)
+  )
+  case XSTileKey => up(XSTileKey).map(_.copy(
+    HasCVMExtension = Some(true),
+    HasBitmapCheckDefault = Some(true)))
+})
+
 class MinimalAliasDebugConfig(n: Int = 1) extends Config(
   new WithNKBL3(512, inclusive = false) ++
     new WithNKBL2(256, inclusive = true) ++
@@ -410,6 +430,22 @@ class DefaultConfig(n: Int = 1) extends Config(
     ++ new BaseConfig(n)
 )
 
+class CVMConfig(n: Int = 1) extends Config(
+  new CVMCompile
+    ++ new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16)
+    ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4)
+    ++ new WithNKBL1D(64, ways = 4)
+    ++ new BaseConfig(n)
+)
+
+class CVMTestConfig(n: Int = 1) extends Config(
+  new CVMTestCompile
+    ++ new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16)
+    ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4)
+    ++ new WithNKBL1D(64, ways = 4)
+    ++ new BaseConfig(n)
+)
+
 class WithCHI extends Config((_, _, _) => {
   case EnableCHI => true
 })

src/main/scala/xiangshan/Bundle.scala

@@ -518,10 +518,33 @@ class TlbHgatpBundle(implicit p: Parameters) extends HgatpStruct {
   }
 }
 
+//add mcvm csr
+class McvmStruct(implicit p: Parameters) extends XSBundle {
+  val BME = UInt(1.W)
+  val CMODE = UInt(1.W)
+  val BCLEAR = UInt(1.W)
+  val BMA = UInt(61.W)
+}
+
+class TlbMcvmBundle(implicit p: Parameters) extends McvmStruct {
+  //val changed = Bool()
+
+  def apply(mcvm_value: UInt): Unit = {
+    require(mcvm_value.getWidth == XLEN)
+    val mc = mcvm_value.asTypeOf(new McvmStruct)
+    BME := mc.BME
+    CMODE := mc.CMODE
+    BCLEAR := mc.BCLEAR
+    BMA := mc.BMA
+    //changed := DataChanged(mc.CMODE)
+  }
+}
+
 class TlbCsrBundle(implicit p: Parameters) extends XSBundle {
   val satp = new TlbSatpBundle()
   val vsatp = new TlbSatpBundle()
   val hgatp = new TlbHgatpBundle()
+  val mcvm = new TlbMcvmBundle()
   val priv = new Bundle {
     val mxr = Bool()
     val sum = Bool()

src/main/scala/xiangshan/PMParameters.scala

@@ -46,6 +46,7 @@ trait HasPMParameters {
   def PMPPmemRanges = p(SoCParamsKey).PmemRanges
   def PMPPmemLowBounds = PMPPmemRanges.unzip._1
   def PMPPmemHighBounds = PMPPmemRanges.unzip._2
+  val PMPKeyIDBits = p(SoCParamsKey).KeyIDBits
   def PMXLEN = p(XLen)
   def pmParams = p(PMParameKey)
   def NumPMP = pmParams.NumPMP

src/main/scala/xiangshan/Parameters.scala

@@ -61,6 +61,8 @@ case class XSCoreParameters
   VLEN: Int = 128,
   ELEN: Int = 64,
   HSXLEN: Int = 64,
+  HasCVMExtension: Option[Boolean] = Some(false),
+  HasBitmapCheckDefault: Option[Boolean] = Some(false),
   HasMExtension: Boolean = true,
   HasCExtension: Boolean = true,
   HasHExtension: Boolean = true,
@@ -586,6 +588,7 @@ trait HasXSParameter {
   def PmemRanges = p(SoCParamsKey).PmemRanges
   def PmemLowBounds = PmemRanges.unzip._1
   def PmemHighBounds = PmemRanges.unzip._2
+  def KeyIDBits = p(SoCParamsKey).KeyIDBits
   final val PageOffsetWidth = 12
   def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC
 
@@ -603,6 +606,8 @@ trait HasXSParameter {
   def hartIdLen = p(MaxHartIdBits)
   val xLen = XLEN
 
+  def HasCVMExtension = coreParams.HasCVMExtension.getOrElse(false)
+  def HasBitmapCheckDefault = coreParams.HasBitmapCheckDefault.getOrElse(false)
   def HasMExtension = coreParams.HasMExtension
   def HasCExtension = coreParams.HasCExtension
   def HasHExtension = coreParams.HasHExtension

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -705,7 +705,11 @@ class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer)
   val pmp_checkers = Seq.fill(DTlbSize)(Module(new PMPChecker(4, leaveHitMux = true)))
   val pmp_check = pmp_checkers.map(_.io)
   for ((p,d) <- pmp_check zip dtlb_pmps) {
-    p.apply(tlbcsr.priv.dmode, pmp.io.pmp, pmp.io.pma, d)
+    if(HasCVMExtension){
+      p.apply(tlbcsr.mcvm.CMODE.asBool, tlbcsr.priv.dmode, pmp.io.pmp, pmp.io.pma, d)
+    }else{
+      p.apply(tlbcsr.priv.dmode, pmp.io.pmp, pmp.io.pma, d)
+    }
     require(p.req.bits.size.getWidth == d.bits.size.getWidth)
   }
 

src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala

@@ -144,6 +144,11 @@ object CSRDefines {
     val Dirty = Value(3.U)
   }
 
+  object BMAField extends CSREnum with WARLApply {
+    val ResetBMA = Value(0.U)
+    val TestBMA = Value("h100000000".U)
+  }
+
   object XLENField extends CSREnum with ROApply {
     val XLEN32 = Value(1.U)
     val XLEN64 = Value(2.U)

src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala

@@ -146,6 +146,7 @@ class TrapEntryEventInput(implicit val p: Parameters) extends Bundle with HasXSP
   val satp = Input(new SatpBundle)
   val vsatp = Input(new SatpBundle)
   val hgatp = Input(new HgatpBundle)
+  val mcvm = Input(new McvmBundle)
   // from mem
   val memExceptionVAddr = Input(UInt(XLEN.W))
   val memExceptionGPAddr = Input(UInt(XLEN.W))

src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala

@@ -19,6 +19,23 @@ import xiangshan.backend.fu.NewCSR.CSRFunc._
 import scala.collection.immutable.SeqMap
 
 trait MachineLevel { self: NewCSR =>
+  // Machine level Custom Read/Write
+  val mcvm = if(HasCVMExtension) Some(Module(new CSRModule("Mcvm", new McvmBundle) {
+    val mcvm_lock = reg.BME.asBool
+    if(!HasBitmapCheckDefault) {
+      reg.BME := Mux(wen && !mcvm_lock, wdata.BME, reg.BME)
+      reg.CMODE := Mux(wen, wdata.CMODE, reg.CMODE)
+      reg.BMA := Mux(wen && !mcvm_lock, wdata.BMA, reg.BMA)
+    } else {
+      reg.BME := 1.U
+      reg.CMODE := 0.U
+      reg.BMA := BMAField.TestBMA
+    }
+    reg.BCLEAR := Mux(reg.BCLEAR.asBool, 0.U, Mux(wen && wdata.BCLEAR.asBool, 1.U, 0.U))
+  })
+    .setAddr(0xBC0))  else  None
+
+
   val mstatus = Module(new MstatusModule)
     .setAddr(CSRs.mstatus)
 
@@ -416,7 +433,8 @@ trait MachineLevel { self: NewCSR =>
     mncause,
     mnstatus,
     mnscratch,
-  ) ++ mhpmevents ++ mhpmcounters
+  ) ++ mhpmevents ++ mhpmcounters ++ (if(HasCVMExtension) Seq(mcvm.get) else Seq())
+
 
   val machineLevelCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_], UInt)] = SeqMap.from(
     machineLevelCSRMods.map(csr => (csr.addr -> (csr.w -> csr.rdata))).iterator
@@ -428,6 +446,13 @@ trait MachineLevel { self: NewCSR =>
 
 }
 
+class McvmBundle extends  CSRBundle {
+  val BME  = RW(63).withReset(0.U)
+  val CMODE  = RW(62).withReset(0.U)
+  val BCLEAR = RW(61).withReset(0.U)
+  val BMA  = BMAField(60,0,null).withReset(BMAField.ResetBMA)
+}
+
 class MstatusBundle extends CSRBundle {
 
   val SIE  = CSRRWField     (1).withReset(0.U)

src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala

@@ -201,6 +201,7 @@ class NewCSR(implicit val p: Parameters) extends Module
       val satp = new SatpBundle
       val vsatp = new SatpBundle
       val hgatp = new HgatpBundle
+      val mcvm = new McvmBundle
       val mxr = Bool()
       val sum = Bool()
       val vmxr = Bool()
@@ -759,7 +760,9 @@ class NewCSR(implicit val p: Parameters) extends Module
         in.satp  := satp.regOut
         in.vsatp := vsatp.regOut
         in.hgatp := hgatp.regOut
-
+        if(HasCVMExtension){in.mcvm  := mcvm.get.regOut}
+        else{in.mcvm  := DontCare}
+
         in.memExceptionVAddr := io.fromMem.excpVA
         in.memExceptionGPAddr := io.fromMem.excpGPA
         in.memExceptionIsForVSnonLeafPTE := io.fromMem.excpIsForVSnonLeafPTE
@@ -857,8 +860,13 @@ class NewCSR(implicit val p: Parameters) extends Module
     (addr >= CSRs.cycle.U) && (addr <= CSRs.hpmcounter31.U)
   )
 
+  val resetSatp = WireInit(false.B)
   // flush
-  val resetSatp = Cat(Seq(satp, vsatp, hgatp).map(_.addr.U === waddrReg)).orR && wenLegalReg // write to satp will cause the pipeline be flushed
+  if(HasCVMExtension){
+    resetSatp := Cat(Seq(satp, vsatp, hgatp, mcvm.get).map(_.addr.U === waddrReg)).orR && wenLegalReg // write to satp will cause the pipeline be flushed
+  }else{
+    resetSatp := Cat(Seq(satp, vsatp, hgatp).map(_.addr.U === waddrReg)).orR && wenLegalReg // write to satp will cause the pipeline be flushed
+  }
 
   val floatStatusOnOff = mstatus.w.wen && (
     mstatus.w.wdataFields.FS === ContextStatus.Off && mstatus.regOut.FS =/= ContextStatus.Off ||
@@ -1268,6 +1276,8 @@ class NewCSR(implicit val p: Parameters) extends Module
   io.tlb.satp := satp.rdata
   io.tlb.vsatp := vsatp.rdata
   io.tlb.hgatp := hgatp.rdata
+  if(HasCVMExtension){io.tlb.mcvm := mcvm.get.rdata}
+  else{io.tlb.mcvm := DontCare}
   io.tlb.mxr  :=  mstatus.regOut.MXR.asBool
   io.tlb.sum  :=  mstatus.regOut.SUM.asBool
   io.tlb.vmxr := vsstatus.regOut.MXR.asBool