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difftest: writeback support for dual core #380

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merged 4 commits into from
May 20, 2024
Merged

difftest: writeback support for dual core #380

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b9ebe86
difftest: add wbint dual-core support
xiaokamikami May 15, 2024
8ac81ec
difftest: fix compile
xiaokamikami May 15, 2024
3bd4c82
difftest: fix vec too long bug
xiaokamikami May 15, 2024
e616437
difftest: fix formate
xiaokamikami May 20, 2024
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19 changes: 11 additions & 8 deletions src/main/scala/Gateway.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -152,13 +152,14 @@ object Gateway {
class GatewayEndpoint(signals: Seq[DifftestBundle], config: GatewayConfig) extends Module {
val in = WireInit(0.U.asTypeOf(MixedVec(signals.map(_.cloneType))))
val in_pack = WireInit(0.U.asTypeOf(MixedVec(signals.map(gen => UInt(gen.getWidth.W)))))
val numcores = signals.count(_.isUniqueIdentifier)
for ((data, id) <- in_pack.zipWithIndex) {
DifftestWiring.addSink(data, s"gateway_$id")
in(id) := data.asTypeOf(in(id).cloneType)
}

val preprocessed = if (config.needPreprocess) {
WireInit(Preprocess(in, config))
WireInit(Preprocess(in, config, numcores))
} else {
WireInit(in)
}
Expand Down Expand Up @@ -249,14 +250,14 @@ class GatewaySinkControl(config: GatewayConfig) extends Bundle {
}

object Preprocess {
def apply(bundles: MixedVec[DifftestBundle], config: GatewayConfig): MixedVec[DifftestBundle] = {
val module = Module(new Preprocess(chiselTypeOf(bundles).toSeq, config))
def apply(bundles: MixedVec[DifftestBundle], config: GatewayConfig, numcores: Int): MixedVec[DifftestBundle] = {
val module = Module(new Preprocess(chiselTypeOf(bundles).toSeq, config, numcores))
module.in := bundles
module.out
}
}

class Preprocess(bundles: Seq[DifftestBundle], config: GatewayConfig) extends Module {
class Preprocess(bundles: Seq[DifftestBundle], config: GatewayConfig, numcores: Int) extends Module {
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val in = IO(Input(MixedVec(bundles)))
val out = IO(Output(MixedVec(bundles)))

Expand All @@ -265,13 +266,15 @@ class Preprocess(bundles: Seq[DifftestBundle], config: GatewayConfig) extends Mo
if (config.hasDutZone || config.isSquash || config.isBatch) {
// Special fix for int writeback. Work for single-core only
if (in.exists(_.desiredCppName == "wb_int")) {
require(in.count(_.isUniqueIdentifier) == 1, "only single-core is supported yet")
if (config.isSquash || config.isBatch) {
require(in.count(_.isUniqueIdentifier) == 1, "only single-core is supported yet")
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}
val writebacks = in.filter(_.desiredCppName == "wb_int").map(_.asInstanceOf[DiffIntWriteback])
val numPhyRegs = writebacks.head.numElements
val wb_int = Reg(Vec(numPhyRegs, UInt(64.W)))
val wb_int = Reg(Vec(numcores, Vec(numPhyRegs, UInt(64.W))))
for (wb <- writebacks) {
when(wb.valid) {
wb_int(wb.address) := wb.data
wb_int(wb.coreid)(wb.address) := wb.data
}
}

Expand All @@ -283,7 +286,7 @@ class Preprocess(bundles: Seq[DifftestBundle], config: GatewayConfig) extends Mo
when(c.valid && c.skip) {
wb_for_skip.valid := true.B
wb_for_skip.address := c.wpdest
wb_for_skip.data := wb_int(c.wpdest)
wb_for_skip.data := wb_int(c.coreid)(c.wpdest)
for (wb <- writebacks) {
when(wb.valid && wb.address === c.wpdest) {
wb_for_skip.data := wb.data
Expand Down