Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

difftest: writeback support for dual core #380

Merged
merged 4 commits into from
May 20, 2024
Merged

difftest: writeback support for dual core #380

Changes from all commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
b9ebe86
difftest: add wbint dual-core support
xiaokamikami May 15, 2024
8ac81ec
difftest: fix compile
xiaokamikami May 15, 2024
3bd4c82
difftest: fix vec too long bug
xiaokamikami May 15, 2024
e616437
difftest: fix formate
xiaokamikami May 20, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
12 changes: 7 additions & 5 deletions src/main/scala/Gateway.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -259,19 +259,21 @@ object Preprocess {
class Preprocess(bundles: Seq[DifftestBundle], config: GatewayConfig) extends Module {
val in = IO(Input(MixedVec(bundles)))
val out = IO(Output(MixedVec(bundles)))

val numCores = bundles.count(_.isUniqueIdentifier)
out := in

if (config.hasDutZone || config.isSquash || config.isBatch) {
// Special fix for int writeback. Work for single-core only
if (in.exists(_.desiredCppName == "wb_int")) {
require(in.count(_.isUniqueIdentifier) == 1, "only single-core is supported yet")
if (config.isSquash || config.isBatch) {
require(numCores == 1, "only single-core is supported yet")
}
val writebacks = in.filter(_.desiredCppName == "wb_int").map(_.asInstanceOf[DiffIntWriteback])
val numPhyRegs = writebacks.head.numElements
val wb_int = Reg(Vec(numPhyRegs, UInt(64.W)))
val wb_int = Reg(Vec(numCores, Vec(numPhyRegs, UInt(64.W))))
for (wb <- writebacks) {
when(wb.valid) {
wb_int(wb.address) := wb.data
wb_int(wb.coreid)(wb.address) := wb.data
}
}

Expand All @@ -283,7 +285,7 @@ class Preprocess(bundles: Seq[DifftestBundle], config: GatewayConfig) extends Mo
when(c.valid && c.skip) {
wb_for_skip.valid := true.B
wb_for_skip.address := c.wpdest
wb_for_skip.data := wb_int(c.wpdest)
wb_for_skip.data := wb_int(c.coreid)(c.wpdest)
for (wb <- writebacks) {
when(wb.valid && wb.address === c.wpdest) {
wb_for_skip.data := wb.data
Expand Down