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Batch: expose extra GatewayIO for FPGA #513

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merged 3 commits into from
Nov 25, 2024
Merged

Batch: expose extra GatewayIO for FPGA #513

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a65fe82
diff : add fpga diff batch io
xiaokamikami Nov 25, 2024
e5971a9
diff: move the interface of the fpga batch to the sink
xiaokamikami Nov 25, 2024
c493953
Batch: expose extra GatewayIO for FPGA
klin02 Nov 25, 2024
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13 changes: 12 additions & 1 deletion src/main/scala/Gateway.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,7 @@ case class GatewayConfig(
def dutBufLen: Int = if (isBatch) batchSize else 1
def maxStep: Int = if (isBatch) batchSize else 1
def stepWidth: Int = log2Ceil(maxStep + 1)
def batchArgByteLen: (Int, Int) = if (isNonBlock) (3600, 400) else (7200, 800)
def batchArgByteLen: (Int, Int) = if (isNonBlock || isFPGA) (3600, 400) else (7200, 800)
def hasDeferredResult: Boolean = isNonBlock || hasInternalStep
def needTraceInfo: Boolean = hasReplay
def needEndpoint: Boolean =
Expand Down Expand Up @@ -266,6 +266,17 @@ object GatewaySink {
case "dpic" => DPIC.batch(template, control, io, config)
case _ => DPIC.batch(template, control, io, config) // Default: DPI-C
}
val out = Option.when(config.isFPGA) {
IO(new Bundle {
val batch = Output(chiselTypeOf(io))
val enable = Output(Bool())
})
}
if (config.isFPGA) {
out.get.batch := io
out.get.enable := control.enable
dontTouch(out.get)
}
}

def collect(config: GatewayConfig): GatewayResult = {
Expand Down