Fix regex for VHDL component instantiations

[javValverde]

• Add comments to the multiline regex
• Extend unittest for vhdl_parser

[LarsAsplund]

Rather than allowing anything between the opening and closing brackets I would suggest extending the previously more restrictive expression with what is needed to pass the new test case:

([\s\w=>,.)(+-'"*/]*)

I cannot recall if the more restrictive expression is there for a reason that is not made explicit in the test cases. For that reason I prefer a more defensive modification.

[javValverde]

Sorry for the delayed reply.
I will modify the regex as you suggested, but I guess there will be other cases in which it won't work

In the mean time I've monkey patched vhdl_parser.py and am matching everything inside the brackets.