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TCL: ad_hpmx_interconnect #1201
TCL: ad_hpmx_interconnect #1201
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} | ||
if {$sys_zynq == 2} { | ||
ad_connect ${interconnect_name}/S00_AXI sys_cips/M_AXI_FPD | ||
} elseif {($p_sel eq "HPM0_FPD") && ($sys_zynq == 2)} { |
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Perhaps nest
} elseif {$sys_zynq == 2} {
if {$p_sel eq "HPM0_FPD"} {
(...)
}
(...)
}
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Thanks for reviewing!
I went with a single line to stay consistent with ad_mem_hpx_interconnect
.
I feel like it's also a bit more readable when we end up having other sys_zynq
values.
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Hi @gastmaier, what do you think of this version? |
Hi Liam, I liked the changes. Thanks, |
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rebased on the lastest branch that includes changes from #1054. summary of the changes: $ git range-diff origin/main lvb/ad_hpmx_interconnect ad_hpmx_interconnect
1: 61c64f6497a0 ! 1: afee12284523 adi_board: add support for other AXI master interfaces
@@ projects/scripts/adi_board.tcl: proc ad_mem_hpx_interconnect {p_sel p_clk p_name
global sys_zynq
- global sys_cpu_interconnect_index
+ global use_smartconnect
- set i_str "M$sys_cpu_interconnect_index"
- if {$sys_cpu_interconnect_index < 10} {
@@ projects/scripts/adi_board.tcl: proc ad_mem_hpx_interconnect {p_sel p_clk p_name
}
+ set i_str [format "M%02d" $interconnect_index]
- set use_smart_connect 1
- # SmartConnect has higher resource utilization and worse timing closure on older families
-@@ projects/scripts/adi_board.tcl: proc ad_cpu_interconnect {p_address p_name {p_intf_name {}}} {
- set use_smart_connect 0
- }
-
- if {$sys_cpu_interconnect_index == 0} {
+ if {$i_str eq "M00"} {
- if {$use_smart_connect == 1} {
+ if {$use_smartconnect == 1} {
- ad_ip_instance smartconnect axi_cpu_interconnect [ list \
+ ad_ip_instance smartconnect $interconnect_name [ list \
NUM_MI 1 \
@@ projects/scripts/adi_board.tcl: proc ad_cpu_interconnect {p_address p_name {p_in
- set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect]
+ set_property CONFIG.NUM_MI $interconnect_index [get_bd_cells $interconnect_name]
- if {$use_smart_connect == 0} {
+ if {$use_smartconnect == 0} {
- ad_connect sys_cpu_clk axi_cpu_interconnect/${i_str}_ACLK
- ad_connect sys_cpu_resetn axi_cpu_interconnect/${i_str}_ARESETN
+ ad_connect sys_cpu_clk $interconnect_name/${i_str}_ACLK
2: 81db033ae062 = 2: cfeb879e32bc adi_board: ad_hpmx_interconnect: add create_bd_addr_seg logs |
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@bia1708 can we trigger the CI on this one? preferably for all projects |
@gastmaier Unfortunately, I can only trigger the CIs for branches inside the analogdevicesinc repo, and not from forks. |
Rework ad_cpu_interconnect to support other master axi interfaces. Add create_bd_addr_seg logs. Signed-off-by: Liam Beguin <[email protected]>
The variable sys_zynq is a global var. Line breaks matter in TCL. Signed-off-by: Jorge Marques <[email protected]>
With the rework of ad_cpu_interconnect to allow other PS AXI manager ports, the interconnect IP name now reflects the AXI manager port name. Rename axi_cpu_interconnect in projects to match the PS AXI manager port name. Signed-off-by: Jorge Marques <[email protected]>
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Propagate approval from CI PR #1416
PR Description
Some custom projects might rely on other PS AXI master interfaces, rework
ad_cpu_interconnect
to allow users to specify other interfaces.For now, I was only able to test this on a zynqmp project, and don't have the full list of interfaces for other platforms, but I'm happy to update the PR.
PR Type
PR Checklist