Skip to content
Verilog Build and Analysis

Rename verilog-compiler.vhdl to verilog-compiler.yml #2

Sign in to view logs

Rename verilog-compiler.vhdl to verilog-compiler.yml

Rename verilog-compiler.vhdl to verilog-compiler.yml #2

Triggered via pull request October 26, 2023 08:56
@jon011235jon011235
synchronize #9
correcting-stupid-error
Status Failure
Total duration 8m 8s
Artifacts –

verilog-compiler.yml

on: pull_request
build-and-analyze
7m 56s
build-and-analyze
Fit to window
Zoom out
Zoom in

Annotations

1 error
build-and-analyze
Process completed with exit code 1.