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Verilog Build and Analysis

Rename verilog-compiler.vhdl to verilog-compiler.yml #3

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Rename verilog-compiler.vhdl to verilog-compiler.yml

Rename verilog-compiler.vhdl to verilog-compiler.yml #3

Run time

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Job Run time
build-and-analyze
11m 18s
11m 18s