Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Rename verilog-compiler.vhdl to verilog-compiler.yml #9

Merged
merged 5 commits into from
Oct 26, 2023

Finishing workflows for now

1f9a2e1
Select commit
Loading
Failed to load commit list.
Merged

Rename verilog-compiler.vhdl to verilog-compiler.yml #9

Finishing workflows for now
1f9a2e1
Select commit
Loading
Failed to load commit list.

Select a check to view from the sidebar