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Rename verilog-compiler.vhdl to verilog-compiler.yml #9

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Oct 26, 2023
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27 changes: 0 additions & 27 deletions .github/actions/verilog-compiler.vhdl

This file was deleted.

14 changes: 0 additions & 14 deletions .github/actions/verilog-linter.yml

This file was deleted.

13 changes: 13 additions & 0 deletions .github/workflows/verilog-linter.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,13 @@
name: Verible linter example
on:
pull_request:
jobs:
lint:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@master
- uses: chipsalliance/verible-linter-action@main
with:
github_token: ${{ secrets.GITHUB_TOKEN }}

# For the future simulating and compiling in modelsim would be great https://purisa.me/blog/testing-hdl-on-github/