Spiller: Detach legacy pass and supply analyses instead #119181

optimisan · 2024-12-09T08:35:21Z

Makes Inline Spiller amenable to the new PM.

optimisan · 2024-12-09T08:35:30Z

Spiller: Detach legacy pass and supply analyses instead #119181 : 2 dependent PRs (#117309 , #119672 ) 👈 (View in Graphite)
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llvmbot · 2024-12-09T08:38:24Z

@llvm/pr-subscribers-llvm-regalloc

Author: Akshat Oke (optimisan)

Changes

Makes Inline Spiller amenable for the new PM.

Full diff: https://github.com/llvm/llvm-project/pull/119181.diff

5 Files Affected:

(modified) llvm/include/llvm/CodeGen/Spiller.h (+14-2)
(modified) llvm/lib/CodeGen/InlineSpiller.cpp (+14-22)
(modified) llvm/lib/CodeGen/RegAllocBasic.cpp (+11-5)
(modified) llvm/lib/CodeGen/RegAllocGreedy.cpp (+3-1)
(modified) llvm/lib/CodeGen/RegAllocPBQP.cpp (+4-1)

diff --git a/llvm/include/llvm/CodeGen/Spiller.h b/llvm/include/llvm/CodeGen/Spiller.h
index 51ad36bc6b1f8b..3132cefeb6c68a 100644
--- a/llvm/include/llvm/CodeGen/Spiller.h
+++ b/llvm/include/llvm/CodeGen/Spiller.h
@@ -19,6 +19,10 @@ class MachineFunction;
 class MachineFunctionPass;
 class VirtRegMap;
 class VirtRegAuxInfo;
+class LiveIntervals;
+class LiveStacks;
+class MachineDominatorTree;
+class MachineBlockFrequencyInfo;
 
 /// Spiller interface.
 ///
@@ -41,12 +45,20 @@ class Spiller {
   virtual ArrayRef<Register> getReplacedRegs() = 0;
 
   virtual void postOptimization() {}
+
+  struct RequiredAnalyses {
+    LiveIntervals &LIS;
+    LiveStacks &LSS;
+    MachineDominatorTree &MDT;
+    const MachineBlockFrequencyInfo &MBFI;
+  };
 };
 
 /// Create and return a spiller that will insert spill code directly instead
 /// of deferring though VirtRegMap.
-Spiller *createInlineSpiller(MachineFunctionPass &Pass, MachineFunction &MF,
-                             VirtRegMap &VRM, VirtRegAuxInfo &VRAI);
+Spiller *createInlineSpiller(const Spiller::RequiredAnalyses &Analyses,
+                             MachineFunction &MF, VirtRegMap &VRM,
+                             VirtRegAuxInfo &VRAI);
 
 } // end namespace llvm
 
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index 64f290f5930a1b..b9768d5c63a5d1 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -75,7 +75,6 @@ RestrictStatepointRemat("restrict-statepoint-remat",
                        cl::desc("Restrict remat for statepoint operands"));
 
 namespace {
-
 class HoistSpillHelper : private LiveRangeEdit::Delegate {
   MachineFunction &MF;
   LiveIntervals &LIS;
@@ -128,15 +127,11 @@ class HoistSpillHelper : private LiveRangeEdit::Delegate {
                       DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns);
 
 public:
-  HoistSpillHelper(MachineFunctionPass &pass, MachineFunction &mf,
-                   VirtRegMap &vrm)
-      : MF(mf), LIS(pass.getAnalysis<LiveIntervalsWrapperPass>().getLIS()),
-        LSS(pass.getAnalysis<LiveStacksWrapperLegacy>().getLS()),
-        MDT(pass.getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree()),
+  HoistSpillHelper(const Spiller::RequiredAnalyses &Analyses,
+                   MachineFunction &mf, VirtRegMap &vrm)
+      : MF(mf), LIS(Analyses.LIS), LSS(Analyses.LSS), MDT(Analyses.MDT),
         VRM(vrm), MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
-        TRI(*mf.getSubtarget().getRegisterInfo()),
-        MBFI(
-            pass.getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI()),
+        TRI(*mf.getSubtarget().getRegisterInfo()), MBFI(Analyses.MBFI),
         IPA(LIS, mf.getNumBlockIDs()) {}
 
   void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
@@ -190,16 +185,12 @@ class InlineSpiller : public Spiller {
   ~InlineSpiller() override = default;
 
 public:
-  InlineSpiller(MachineFunctionPass &Pass, MachineFunction &MF, VirtRegMap &VRM,
-                VirtRegAuxInfo &VRAI)
-      : MF(MF), LIS(Pass.getAnalysis<LiveIntervalsWrapperPass>().getLIS()),
-        LSS(Pass.getAnalysis<LiveStacksWrapperLegacy>().getLS()),
-        MDT(Pass.getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree()),
+  InlineSpiller(const Spiller::RequiredAnalyses &Analyses, MachineFunction &MF,
+                VirtRegMap &VRM, VirtRegAuxInfo &VRAI)
+      : MF(MF), LIS(Analyses.LIS), LSS(Analyses.LSS), MDT(Analyses.MDT),
         VRM(VRM), MRI(MF.getRegInfo()), TII(*MF.getSubtarget().getInstrInfo()),
-        TRI(*MF.getSubtarget().getRegisterInfo()),
-        MBFI(
-            Pass.getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI()),
-        HSpiller(Pass, MF, VRM), VRAI(VRAI) {}
+        TRI(*MF.getSubtarget().getRegisterInfo()), MBFI(Analyses.MBFI),
+        HSpiller(Analyses, MF, VRM), VRAI(VRAI) {}
 
   void spill(LiveRangeEdit &) override;
   ArrayRef<Register> getSpilledRegs() override { return RegsToSpill; }
@@ -237,10 +228,11 @@ Spiller::~Spiller() = default;
 
 void Spiller::anchor() {}
 
-Spiller *llvm::createInlineSpiller(MachineFunctionPass &Pass,
-                                   MachineFunction &MF, VirtRegMap &VRM,
-                                   VirtRegAuxInfo &VRAI) {
-  return new InlineSpiller(Pass, MF, VRM, VRAI);
+Spiller *
+llvm::createInlineSpiller(const InlineSpiller::RequiredAnalyses &Analyses,
+                          MachineFunction &MF, VirtRegMap &VRM,
+                          VirtRegAuxInfo &VRAI) {
+  return new InlineSpiller(Analyses, MF, VRM, VRAI);
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp
index c05aa1e40e4779..f3f34f890be11e 100644
--- a/llvm/lib/CodeGen/RegAllocBasic.cpp
+++ b/llvm/lib/CodeGen/RegAllocBasic.cpp
@@ -22,6 +22,7 @@
 #include "llvm/CodeGen/LiveRegMatrix.h"
 #include "llvm/CodeGen/LiveStacks.h"
 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
+#include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/Passes.h"
@@ -187,6 +188,7 @@ void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.addRequired<ProfileSummaryInfoWrapperPass>();
   AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
   AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
+  AU.addRequired<MachineDominatorTreeWrapperPass>();
   AU.addRequiredID(MachineDominatorsID);
   AU.addPreservedID(MachineDominatorsID);
   AU.addRequired<MachineLoopInfoWrapperPass>();
@@ -310,16 +312,20 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
                     << "********** Function: " << mf.getName() << '\n');
 
   MF = &mf;
+  auto &MBFI = getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
+  auto &LiveStks = getAnalysis<LiveStacksWrapperLegacy>().getLS();
+  auto &MDT = getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+
   RegAllocBase::init(getAnalysis<VirtRegMapWrapperLegacy>().getVRM(),
                      getAnalysis<LiveIntervalsWrapperPass>().getLIS(),
                      getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM());
-  VirtRegAuxInfo VRAI(
-      *MF, *LIS, *VRM, getAnalysis<MachineLoopInfoWrapperPass>().getLI(),
-      getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI(),
-      &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI());
+  VirtRegAuxInfo VRAI(*MF, *LIS, *VRM,
+                      getAnalysis<MachineLoopInfoWrapperPass>().getLI(), MBFI,
+                      &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI());
   VRAI.calculateSpillWeightsAndHints();
 
-  SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM, VRAI));
+  SpillerInstance.reset(
+      createInlineSpiller({*LIS, LiveStks, MDT, MBFI}, *MF, *VRM, VRAI));
 
   allocatePhysRegs();
   postOptimization();
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index d3a7f4cb6f1206..033f048ca7499b 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2733,6 +2733,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
   Bundles = &getAnalysis<EdgeBundlesWrapperLegacy>().getEdgeBundles();
   SpillPlacer = &getAnalysis<SpillPlacementWrapperLegacy>().getResult();
   DebugVars = &getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
+  auto &LSS = getAnalysis<LiveStacksWrapperLegacy>().getLS();
 
   initializeCSRCost();
 
@@ -2755,7 +2756,8 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
                                                                       *this);
 
   VRAI = std::make_unique<VirtRegAuxInfo>(*MF, *LIS, *VRM, *Loops, *MBFI);
-  SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM, *VRAI));
+  SpillerInstance.reset(
+      createInlineSpiller({*LIS, LSS, *DomTree, *MBFI}, *MF, *VRM, *VRAI));
 
   VRAI->calculateSpillWeightsAndHints();
 
diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp
index 696c312e4ba00a..e230a1be95c9fa 100644
--- a/llvm/lib/CodeGen/RegAllocPBQP.cpp
+++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp
@@ -794,6 +794,9 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
   MachineBlockFrequencyInfo &MBFI =
       getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
 
+  auto &LiveStks = getAnalysis<LiveStacksWrapperLegacy>().getLS();
+  auto &MDT = getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+
   VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
 
   PBQPVirtRegAuxInfo VRAI(
@@ -807,7 +810,7 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
   VirtRegAuxInfo DefaultVRAI(
       MF, LIS, VRM, getAnalysis<MachineLoopInfoWrapperPass>().getLI(), MBFI);
   std::unique_ptr<Spiller> VRegSpiller(
-      createInlineSpiller(*this, MF, VRM, DefaultVRAI));
+      createInlineSpiller({LIS, LiveStks, MDT, MBFI}, MF, VRM, DefaultVRAI));
 
   MF.getRegInfo().freezeReservedRegs();

)" This reverts commit a531800.

llvm-ci · 2025-01-10T09:05:54Z

LLVM Buildbot has detected a new failure on builder llvm-clang-x86_64-expensive-checks-debian running on gribozavr4 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/16/builds/11748

Here is the relevant piece of the build log for the reference

Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: tools/llvm-gsymutil/ARM_AArch64/macho-merged-funcs-dwarf.yaml' FAILED ********************
Exit Code: 1

Command Output (stdout):
--
Input file: /b/1/llvm-clang-x86_64-expensive-checks-debian/build/test/tools/llvm-gsymutil/ARM_AArch64/Output/macho-merged-funcs-dwarf.yaml.tmp.dSYM
Output file (aarch64): /b/1/llvm-clang-x86_64-expensive-checks-debian/build/test/tools/llvm-gsymutil/ARM_AArch64/Output/macho-merged-funcs-dwarf.yaml.tmp.default.gSYM
Loaded 3 functions from DWARF.
Loaded 3 functions from symbol table.
warning: same address range contains different debug info. Removing:
[0x0000000000000248 - 0x0000000000000270): Name=0x00000047
addr=0x0000000000000248, file=  3, line=  5
addr=0x0000000000000254, file=  3, line=  7
addr=0x0000000000000258, file=  3, line=  9
addr=0x000000000000025c, file=  3, line=  8
addr=0x0000000000000260, file=  3, line= 11
addr=0x0000000000000264, file=  3, line= 10
addr=0x0000000000000268, file=  3, line=  6


In favor of this one:
[0x0000000000000248 - 0x0000000000000270): Name=0x00000030
addr=0x0000000000000248, file=  2, line=  5
addr=0x0000000000000254, file=  2, line=  7
addr=0x0000000000000258, file=  2, line=  9
addr=0x000000000000025c, file=  2, line=  8
addr=0x0000000000000260, file=  2, line= 11
addr=0x0000000000000264, file=  2, line= 10
addr=0x0000000000000268, file=  2, line=  6


warning: same address range contains different debug info. Removing:
[0x0000000000000248 - 0x0000000000000270): Name=0x00000030
addr=0x0000000000000248, file=  2, line=  5
addr=0x0000000000000254, file=  2, line=  7
addr=0x0000000000000258, file=  2, line=  9
addr=0x000000000000025c, file=  2, line=  8
addr=0x0000000000000260, file=  2, line= 11
addr=0x0000000000000264, file=  2, line= 10
addr=0x0000000000000268, file=  2, line=  6


In favor of this one:
[0x0000000000000248 - 0x0000000000000270): Name=0x00000001
addr=0x0000000000000248, file=  1, line=  5
addr=0x0000000000000254, file=  1, line=  7
addr=0x0000000000000258, file=  1, line=  9
addr=0x000000000000025c, file=  1, line=  8
addr=0x0000000000000260, file=  1, line= 11
addr=0x0000000000000264, file=  1, line= 10
...

Makes Inline Spiller amenable to the new PM.

…9181)" (#122665) Makes Inline Spiller amenable to the new PM. This reapplies commit a531800 reverted because of two unused private members reported on sanitizer bots.

Makes Inline Spiller amenable to the new PM.

…m#119181)" (llvm#122665) Makes Inline Spiller amenable to the new PM. This reapplies commit a531800 reverted because of two unused private members reported on sanitizer bots.

Makes Inline Spiller amenable to the new PM.

…m#119181)" (llvm#122665) Makes Inline Spiller amenable to the new PM. This reapplies commit a531800 reverted because of two unused private members reported on sanitizer bots.

This was referenced Dec 9, 2024

[CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to NPM #118462

Open

[CodeGen][NewPM] Port RegAllocEvictionAdvisor analysis to NPM #117309

Open

optimisan changed the title ~~Spiller: Deatach legacy pass and supply analyses instead~~ Spiller: Detach legacy pass and supply analyses instead Dec 9, 2024

optimisan marked this pull request as ready for review December 9, 2024 08:37

llvmbot added the llvm:regalloc label Dec 9, 2024

optimisan requested review from ellishg, paperchalice, cdevadas and arsenm December 9, 2024 09:14

arsenm requested a review from aeubanks December 9, 2024 15:37

arsenm approved these changes Dec 9, 2024

View reviewed changes

aeubanks approved these changes Dec 9, 2024

View reviewed changes

optimisan force-pushed the users/Akshat-Oke/12-03-_codegen_newpm_port_regallocpriorityadvisor_analysis_to_npm branch from ea0cf8d to 2054a81 Compare December 11, 2024 11:01

optimisan force-pushed the users/Akshat-Oke/12-09-spiller_deatach_legacy_pass_and_supply_analyses_instead branch from 5b4e72f to d13349b Compare December 11, 2024 11:01

This was referenced Dec 11, 2024

[CodeGen][NewPM] Port RegAllocGreedy to NPM #119540

Open

NFC: Move RegAlloc headers to include dir #119672

Closed

optimisan force-pushed the users/Akshat-Oke/12-03-_codegen_newpm_port_regallocpriorityadvisor_analysis_to_npm branch from 2054a81 to 7e882f7 Compare December 19, 2024 11:32

optimisan force-pushed the users/Akshat-Oke/12-09-spiller_deatach_legacy_pass_and_supply_analyses_instead branch from d13349b to f336e93 Compare December 19, 2024 11:33

optimisan force-pushed the users/Akshat-Oke/12-03-_codegen_newpm_port_regallocpriorityadvisor_analysis_to_npm branch from 7e882f7 to d10dca7 Compare January 1, 2025 06:38

optimisan force-pushed the users/Akshat-Oke/12-09-spiller_deatach_legacy_pass_and_supply_analyses_instead branch from f336e93 to 02202be Compare January 1, 2025 06:38

optimisan mentioned this pull request Jan 1, 2025

[Support] Recycler: Enforce minimum allocation size #121425

Merged

optimisan force-pushed the users/Akshat-Oke/12-03-_codegen_newpm_port_regallocpriorityadvisor_analysis_to_npm branch from d10dca7 to d871465 Compare January 1, 2025 06:55

optimisan force-pushed the users/Akshat-Oke/12-09-spiller_deatach_legacy_pass_and_supply_analyses_instead branch from 02202be to 8151817 Compare January 1, 2025 06:55

optimisan force-pushed the users/Akshat-Oke/12-03-_codegen_newpm_port_regallocpriorityadvisor_analysis_to_npm branch from d871465 to 9c2ca75 Compare January 1, 2025 07:07

optimisan removed request for rafaelauler, ellishg, ayermolo, yota9, ftynse, makslevental, stellaraccident, grypp, antiagainst, kuhar, matthias-springer, JDevlieghere, Endilll, nikic, a team, paperchalice and cdevadas January 9, 2025 10:20

optimisan merged commit a531800 into main Jan 10, 2025
9 of 13 checks passed

optimisan deleted the users/Akshat-Oke/12-09-spiller_deatach_legacy_pass_and_supply_analyses_instead branch January 10, 2025 06:16

optimisan added a commit that referenced this pull request Jan 10, 2025

Revert "Spiller: Detach legacy pass and supply analyses instead (#119181

f11be66

)" This reverts commit a531800.

BaiXilin pushed a commit to BaiXilin/llvm-fix-vnni-instr-types that referenced this pull request Jan 12, 2025

Spiller: Detach legacy pass and supply analyses instead (llvm#119181)

fae2d87

Makes Inline Spiller amenable to the new PM.

optimisan mentioned this pull request Jan 13, 2025

Reapply "Spiller: Detach legacy pass and supply analyses instead (#119181)" #122665

Merged

Mel-Chen pushed a commit to Mel-Chen/llvm-project that referenced this pull request Jan 13, 2025

Spiller: Detach legacy pass and supply analyses instead (llvm#119181)

c7b796e

Makes Inline Spiller amenable to the new PM.

DKLoehr pushed a commit to DKLoehr/llvm-project that referenced this pull request Jan 17, 2025

Spiller: Detach legacy pass and supply analyses instead (llvm#119181)

153f36e

Makes Inline Spiller amenable to the new PM.

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Spiller: Detach legacy pass and supply analyses instead #119181

Spiller: Detach legacy pass and supply analyses instead #119181

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