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o1vm/riscv32: implement M type instruction Remu #2808

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merged 1 commit into from
Dec 3, 2024

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dannywillems
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@@ -2219,7 +2219,17 @@ pub fn interpret_mtype<Env: InterpreterEnv>(env: &mut Env, instr: MInstruction)
env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32));
}
MInstruction::Remu => {
unimplemented!("Remu")
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it would be nice to comment the implementation from https://msyksphinz-self.github.io/riscv-isadoc/html/rvm.html

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we can add docs in future prs

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codecov bot commented Nov 21, 2024

Codecov Report

Attention: Patch coverage is 0% with 11 lines in your changes missing coverage. Please review.

Project coverage is 71.91%. Comparing base (e084008) to head (4c5bff9).
Report is 3 commits behind head on master.

Files with missing lines Patch % Lines
o1vm/src/interpreters/riscv32im/interpreter.rs 0.00% 11 Missing ⚠️
Additional details and impacted files
@@            Coverage Diff             @@
##           master    #2808      +/-   ##
==========================================
- Coverage   71.92%   71.91%   -0.02%     
==========================================
  Files         257      257              
  Lines       60275    60287      +12     
==========================================
- Hits        43355    43353       -2     
- Misses      16920    16934      +14     

☔ View full report in Codecov by Sentry.
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Base automatically changed from dw/riscv32-impl-m-type-divu to master December 3, 2024 15:32
@dannywillems dannywillems merged commit 31a9b3f into master Dec 3, 2024
7 of 8 checks passed
@dannywillems dannywillems deleted the dw/riscv32-impl-m-type-remu branch December 3, 2024 20:06
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2 participants