axis tb fix

pulp-platform · Feb 15, 2024 · a208107 · a208107
1 parent 7072a3f
commit a208107
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Showing 5 changed files with 33 additions and 23 deletions.
diff --git a/idma.mk b/idma.mk
@@ -23,7 +23,8 @@ SHELL := /bin/bash
 IDMA_BASE_IDS    ?= \
 					rw_axi \
 					r_obi_w_axi \
-					r_axi_w_obi
+					r_axi_w_obi \
+					rw_axi_rw_axis
 IDMA_OCCAMY_IDS  ?= \
 					r_obi_rw_init_w_axi \
 					r_axi_rw_init_rw_obi

diff --git a/jobs/jobs.json b/jobs/jobs.json
@@ -194,6 +194,16 @@
         "testbench": "tb_idma_nd_midend",
         "synth_top": "idma_nd_midend_synth"
     },
+    "rw_axi_rw_axis": {
+        "jobs" : {
+            "simple"          : "backend_rw_axi/simple.txt"
+        },
+        "params" : {
+        },
+        "proc_id" : "rw_axi_rw_axis",
+        "testbench" : "tb_idma_backend_rw_axi_rw_axis",
+        "synth_top" : "idma_backend_synth_rw_axi_rw_axis"
+    },
     "desc64": {
         "jobs" : {
             "simple" : "jobs.json"

diff --git a/src/db/idma_axi_stream.yml b/src/db/idma_axi_stream.yml
@@ -15,12 +15,12 @@ write_meta_channel: "t_chan"
 read_meta_channel: "t_chan"
 combined_aw_and_w: "true"
 read_slave: "true"
-meta_channel_width: "localparam int unsigned axi_stream_t_chan_width = $bits(axi_stream_t_chan_t);"
+meta_channel_width: "localparam int unsigned axis_t_chan_width = $bits(axis_t_chan_t);"
 typedefs: |
-    `IDMA_AXI_STREAM_TYPEDEF_S_CHAN_T(axi_stream_t_chan_t, data_t, strb_t, strb_t, id_t, id_t, user_t)
+    `IDMA_AXI_STREAM_TYPEDEF_S_CHAN_T(axis_t_chan_t, data_t, strb_t, strb_t, id_t, id_t, user_t)
 
-    `IDMA_AXI_STREAM_TYPEDEF_REQ_T(axi_stream_req_t, axi_stream_t_chan_t)
-    `IDMA_AXI_STREAM_TYPEDEF_RSP_T(axi_stream_rsp_t)
+    `IDMA_AXI_STREAM_TYPEDEF_REQ_T(axis_req_t, axis_t_chan_t)
+    `IDMA_AXI_STREAM_TYPEDEF_RSP_T(axis_rsp_t)
 read_bridge_template: |
     // AXI Stream to OBI Read Bridge
     obi_req_t axi_stream_obi_read_req;
@@ -30,11 +30,10 @@ read_bridge_template: |
     assign axi_stream_obi_read_req.a.wdata = '0;
     assign axi_stream_obi_read_req.a.be    = '1;
 
-    assign axi_stream_obi_read_req.r_ready = axi_stream_read_req.tready;
-    assign axi_stream_read_rsp.tvalid      = axi_stream_obi_read_rsp.r_valid;
+    assign axi_stream_obi_read_req.r_ready = axis_read_req.tvalid;
+    assign axis_read_rsp.tready      = axi_stream_obi_read_rsp.r_valid;
     always_comb begin
-        axi_stream_read_rsp.t      = '0;
-        axi_stream_read_rsp.t.data = axi_stream_obi_read_rsp.r.rdata;
+        axis_read_req.t.data = axi_stream_obi_read_rsp.r.rdata;
     end
 
     int unsigned launched_axis_jobs;
@@ -124,14 +123,14 @@ write_bridge_template: |
     obi_req_t axi_stream_obi_write_req;
     obi_rsp_t axi_stream_obi_write_rsp;
 
-    assign axi_stream_obi_write_req.a_req   = axi_stream_write_req.tvalid;
+    assign axi_stream_obi_write_req.a_req   = axis_write_req.tvalid;
     assign axi_stream_obi_write_req.a.we    = 1'b1;
-    assign axi_stream_obi_write_req.a.wdata = axi_stream_write_req.t.data;
-    assign axi_stream_obi_write_req.a.be    = axi_stream_write_req.t.keep;
-    assign axi_stream_obi_write_req.a.aid   = axi_stream_write_req.t.id;
+    assign axi_stream_obi_write_req.a.wdata = axis_write_req.t.data;
+    assign axi_stream_obi_write_req.a.be    = axis_write_req.t.keep;
+    assign axi_stream_obi_write_req.a.aid   = axis_write_req.t.id;
     assign axi_stream_obi_write_req.r_ready = 1'b1;
 
-    assign axi_stream_write_rsp.tready = axi_stream_obi_write_rsp.a_gnt;
+    assign axis_write_rsp.tready = axi_stream_obi_write_rsp.a_gnt;
 
     initial begin
         string job_file;
@@ -172,12 +171,12 @@ write_bridge_template: |
             axi_stream_obi_write_req.a.addr = address;
 
             // Wait for first write
-            wait(axi_stream_write_req.tvalid);
+            wait(axis_write_req.tvalid);
             next_job = 1'b0;
             while(!next_job) begin
                 @(posedge clk);
-                if(axi_stream_write_req.tvalid && axi_stream_write_rsp.tready) begin
-                    next_job = axi_stream_write_req.t.last;
+                if(axis_write_req.tvalid && axis_write_rsp.tready) begin
+                    next_job = axis_write_req.t.last;
 
                     // Increment address
                     address += StrbWidth;

diff --git a/test/include/tb_tasks.svh b/test/include/tb_tasks.svh
@@ -163,16 +163,16 @@
         input byte_t byte_i,
         input addr_t addr_i
     );
-        i_axi_stream_axi_sim_mem.mem[addr_i] = byte_i;
+        i_axis_axi_sim_mem.mem[addr_i] = byte_i;
     endtask
 
     // read a byte from the AXI Stream AXI-attached memory
     task read_byte_axi_stream_axi_mem (
         output byte_t byte_o,
         input  addr_t addr_i
     );
-        if (i_axi_stream_axi_sim_mem.mem.exists(addr_i))
-            byte_o = i_axi_stream_axi_sim_mem.mem[addr_i];
+        if (i_axis_axi_sim_mem.mem.exists(addr_i))
+            byte_o = i_axis_axi_sim_mem.mem[addr_i];
         else
             byte_o = '1;
     endtask

diff --git a/test/tpl/tb_idma_backend.sv.tpl b/test/tpl/tb_idma_backend.sv.tpl
@@ -92,7 +92,7 @@ module tb_idma_backend_${name_uniqueifier} import idma_pkg::*; #(
 
     // ${database['axi']['full_name']} typedefs
 ${database['axi']['typedefs']}
-% if ('obi' in used_protocols) or ('axi_stream' in used_protocols):
+% if ('obi' in used_protocols) or ('axis' in used_protocols):
     // ${database['obi']['full_name']} typedefs
 ${database['obi']['typedefs']}
 % endif
@@ -1086,8 +1086,8 @@ axi_rsp_mem       )
             // Check if corresponding writes went through
             case(now.dst_protocol)
     % for protocol in used_write_protocols:
-            idma_pkg::${database[protocol]['protocol_enum']}:
-        % if (protocol == 'axi') or (protocol == 'axi_stream') or (protocol == 'obi') or (protocol == 'init'):
+        idma_pkg::${database[protocol]['protocol_enum']}:
+        % if (protocol == 'axi') or (protocol == 'axis') or (protocol == 'obi') or (protocol == 'init'):
                 id = now.id;
         % elif protocol == 'axi_lite':
                 id = now.id[2:0];