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Fix AXI stream sim
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@thommythomaso
thommythomaso committed Feb 15, 2024
1 parent a208107 commit e781d79
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Showing 15 changed files with 179 additions and 104 deletions.
14 changes: 14 additions & 0 deletions jobs/jobs.json
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Expand Up @@ -199,6 +199,20 @@
"simple" : "backend_rw_axi/simple.txt"
},
"params" : {
"DataWidth" : 32,
"AddrWidth" : 32,
"UserWidth" : 1,
"AxiIdWidth" : 12,
"NumAxInFlight" : 3,
"BufferDepth" : 3,
"TFLenWidth" : 32,
"MemSysDepth" : 0,
"CombinedShifter" : 0,
"MaskInvalidData" : 1,
"RAWCouplingAvail" : 0,
"HardwareLegalizer" : 1,
"RejectZeroTransfers" : 1,
"ErrorHandling" : 0
},
"proc_id" : "rw_axi_rw_axis",
"testbench" : "tb_idma_backend_rw_axi_rw_axis",
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18 changes: 9 additions & 9 deletions src/backend/idma_axis_read.sv
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Expand Up @@ -50,9 +50,9 @@ module idma_axis_read #(
output logic read_meta_ready_o,

/// AXI Stream read manager port request
output read_req_t read_req_o,
input read_req_t read_req_i,
/// AXI Stream read manager port response
input read_rsp_t read_rsp_i,
output read_rsp_t read_rsp_o,

/// Response channel valid and ready
output logic r_chan_ready_o,
Expand Down Expand Up @@ -105,7 +105,7 @@ module idma_axis_read #(

// a barrel shifter is a concatenation of the same array with twice and a normal
// shift. Optimized for Synopsys DesignWare.
assign buffer_in_o = read_rsp_i.t.data;
assign buffer_in_o = read_req_i.t.data;
assign mask_in = {read_aligned_in_mask, read_aligned_in_mask} >> r_dp_req_i.shift;


Expand All @@ -115,24 +115,24 @@ module idma_axis_read #(
// the buffer can be pushed to if all the masked FIFO buffers (mask_in) are ready.
assign in_ready = &(buffer_in_ready_i | ~mask_in);
// the read can accept data if the buffer is ready and the response channel is ready
assign read_req_o.tready = in_ready & r_dp_rsp_ready_i & r_dp_req_valid_i;
assign read_rsp_o.tready = in_ready & r_dp_rsp_ready_i & r_dp_req_valid_i;

// once valid data is applied, it can be pushed in all the selected (mask_in) buffers
// be sure the response channel is ready
assign in_valid = read_rsp_i.tvalid & in_ready & r_dp_rsp_ready_i;
assign in_valid = read_req_i.tvalid & in_ready & r_dp_rsp_ready_i;
assign buffer_in_valid_o = in_valid ? mask_in : '0;

// r_dp_ready_o is triggered by the last element arriving from the read
assign r_dp_req_ready_o = r_dp_req_valid_i & r_dp_rsp_ready_i & read_rsp_i.tvalid & in_ready;
assign r_chan_ready_o = read_req_o.tready;
assign r_chan_valid_o = read_rsp_i.tvalid;
assign r_dp_req_ready_o = r_dp_req_valid_i & r_dp_rsp_ready_i & read_req_i.tvalid & in_ready;
assign r_chan_ready_o = read_rsp_o.tready;
assign r_chan_valid_o = read_req_i.tvalid;

// connect r_dp response payload
assign r_dp_rsp_o.resp = '0;
assign r_dp_rsp_o.last = 1'b1;
assign r_dp_rsp_o.first = 1'b1;

// r_dp_valid_o is triggered once the last element is here or an error occurs
assign r_dp_rsp_valid_o = read_rsp_i.tvalid & in_ready;
assign r_dp_rsp_valid_o = read_req_i.tvalid & in_ready;

endmodule
4 changes: 2 additions & 2 deletions src/backend/idma_axis_write.sv
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Expand Up @@ -124,7 +124,7 @@ module idma_axis_write #(
// always_comb process implements masking of invalid data
always_comb begin : proc_mask
// defaults
write_req_o.t = aw_req_i.axi_stream.t_chan;
write_req_o.t = aw_req_i.axis.t_chan;
buffer_data_masked = '0;
// control the write to the bus apply data to the bus only if data should be written
if (ready_to_write == 1'b1 & !dp_poison_i) begin
Expand All @@ -143,7 +143,7 @@ module idma_axis_write #(
// not used signal
assign buffer_data_masked = '0;
// simpler: direct connection
assign write_req_o.t = aw_req_i.axi_stream.t_chan;
assign write_req_o.t = aw_req_i.axis.t_chan;
assign write_req_o.t.data = buffer_out_i;
assign write_req_o.t.keep = dp_poison_i ? '0 : mask_out;
end
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21 changes: 21 additions & 0 deletions src/backend/tpl/idma_backend.sv.tpl
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Expand Up @@ -122,17 +122,33 @@ module idma_backend_${name_uniqueifier} #(
% for protocol in used_read_protocols:

/// ${database[protocol]['full_name']} read request
% if database[protocol]['passive_req'] == 'true':
input ${protocol}\
% if database[protocol]['read_slave'] == 'true':
_read\
% endif
_req_t ${protocol}_read_req_i,
% else:
output ${protocol}\
% if database[protocol]['read_slave'] == 'true':
_read\
% endif
_req_t ${protocol}_read_req_o,
% endif
/// ${database[protocol]['full_name']} read response
% if database[protocol]['passive_req'] == 'true':
output ${protocol}\
% if database[protocol]['read_slave'] == 'true':
_read\
% endif
_rsp_t ${protocol}_read_rsp_o,
% else:
input ${protocol}\
% if database[protocol]['read_slave'] == 'true':
_read\
% endif
_rsp_t ${protocol}_read_rsp_i,
% endif
% endfor
% for protocol in used_write_protocols:

Expand Down Expand Up @@ -713,8 +729,13 @@ _rsp_t ${protocol}_write_rsp_i,
.testmode_i ( testmode_i )\
% for protocol in used_read_protocols:
,
% if database[protocol]['passive_req'] == 'true':
.${protocol}_read_req_i ( ${protocol}_read_req_i ),
.${protocol}_read_rsp_o ( ${protocol}_read_rsp_o )\
% else:
.${protocol}_read_req_o ( ${protocol}_read_req_o ),
.${protocol}_read_rsp_i ( ${protocol}_read_rsp_i )\
% endif
% endfor
% for protocol in used_write_protocols:
,
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5 changes: 5 additions & 0 deletions src/backend/tpl/idma_backend_synth.sv.tpl
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Expand Up @@ -338,8 +338,13 @@ ${p}_${database[p]['write_meta_channel']}_width\
.eh_req_ready_o ( eh_req_ready_o )\
% for protocol in used_read_protocols:
,
% if database[protocol]['passive_req'] == 'true':
.${protocol}_read_req_i ( ${protocol}_read_req ),
.${protocol}_read_rsp_o ( ${protocol}_read_rsp )\
% else:
.${protocol}_read_req_o ( ${protocol}_read_req ),
.${protocol}_read_rsp_i ( ${protocol}_read_rsp )\
% endif
% endfor
% for protocol in used_write_protocols:
,
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16 changes: 16 additions & 0 deletions src/backend/tpl/idma_transport_layer.sv.tpl
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Expand Up @@ -75,17 +75,33 @@ module idma_transport_layer_${name_uniqueifier} #(
% for protocol in used_read_protocols:

/// ${database[protocol]['full_name']} read request
% if database[protocol]['passive_req'] == 'true':
input ${protocol}\
% if database[protocol]['read_slave'] == 'true':
_read\
% endif
_req_t ${protocol}_read_req_i,
% else:
output ${protocol}\
% if database[protocol]['read_slave'] == 'true':
_read\
% endif
_req_t ${protocol}_read_req_o,
% endif
/// ${database[protocol]['full_name']} read response
% if database[protocol]['passive_req'] == 'true':
output ${protocol}\
% if database[protocol]['read_slave'] == 'true':
_read\
% endif
_rsp_t ${protocol}_read_rsp_o,
% else:
input ${protocol}\
% if database[protocol]['read_slave'] == 'true':
_read\
% endif
_rsp_t ${protocol}_read_rsp_i,
% endif
% endfor
% for protocol in used_write_protocols:

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1 change: 1 addition & 0 deletions src/db/idma_axi.yml
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Expand Up @@ -17,6 +17,7 @@ read_meta_channel: "ar_chan"
write_meta_channel: "aw_chan"
combined_aw_and_w: "false"
read_slave: "false"
passive_req: "false"
read_meta_channel_width: "localparam int unsigned axi_ar_chan_width = axi_pkg::ar_width(AddrWidth, AxiIdWidth, UserWidth);"
write_meta_channel_width: "localparam int unsigned axi_aw_chan_width = axi_pkg::aw_width(AddrWidth, AxiIdWidth, UserWidth);"
typedefs: |
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1 change: 1 addition & 0 deletions src/db/idma_axi_lite.yml
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Expand Up @@ -15,6 +15,7 @@ read_meta_channel: "ar_chan"
write_meta_channel: "aw_chan"
combined_aw_and_w: "false"
read_slave: "false"
passive_req: "false"
read_meta_channel_width: |
"localparam int unsigned axi_lite_ar_chan_width = $bits(axi_lite_ar_chan_t);"
write_meta_channel_width: |
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