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risc

Here are 265 public repositories matching this topic...

Ripes

mortbopet / Ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

education processor-architecture qt simulator computer-architecture risc risc-v cpu-emulator

Updated Dec 2, 2024
C++

RVVM

LekKit / RVVM

The RISC-V Virtual Machine

Updated Dec 1, 2024
C

chipsalliance / Cores-VeeR-EH1

VeeR EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer

Updated May 29, 2023
SystemVerilog

michaeljclark / rv8

RISC-V simulator for x86-64

linux emulator metadata simulator disassembler histogram riscv isa risc binary-translation macro-op-fusion rv-sys rv-sim rv-meta rv-jit rv8

Updated Feb 5, 2022
C++

jupiter

andrescv / jupiter

RISC-V Assembler and Runtime Simulator

education simulator runtime asm assembler riscv risc risc-v rv32 riscv-simulator runtime-simulator rv32g

Updated Jun 8, 2024
JavaScript

mipt-mips

MIPT-ILab / mipt-mips

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

simulator cpu pipeline mips simulation mipt cpu-cache optimizations computer-architecture risc cpu-model risc-v branch-prediction computer-architecture-lesson branch-predictor clock-precise pre-silicon mips-binutils prediction-algorithms

Updated Jun 11, 2022
C++

Wren6991 / RISCBoy

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

cpu fpga gameboy pcb risc risc-v

Updated Jul 4, 2023
C

kvakil / venus

RISC-V instruction set simulator built for education

education assembler risc risc-v

Updated Apr 2, 2022
Kotlin

liuqdev / 8-bits-RISC-CPU-Verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

cpu fsm verilog risc

Updated Jan 20, 2019
Verilog

Mariotti94 / WebRISC-V

WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]

php education processor-architecture simulator pipeline assembly computer-architecture risc risc-v pipeline-simulation-environment

Updated Jan 15, 2024
PHP

Vulcan

vmmc2 / Vulcan

RISC-V Instruction Set Simulator (Built for education).

education simulator assembly computer-architecture risc risc-v

Updated Jan 24, 2022
Dart

nikolaydubina / go-hackers-delight

"Hacker's Delight" in Go

c binary book assembly logic bits showcase risc

Updated Sep 20, 2024
Go

mrisc32

mrisc32 / mrisc32

MRSIC32 ISA documentation and development

cpu isa risc mrisc32

Updated Sep 2, 2023
TeX

AluVM / rust-aluvm

Rust implementation of AluVM (RISC functional machine)

rust microcontrollers functional-programming virtual-machine smart-contracts blockchain embedded-systems risc instruction-set-architecture edge-computing

Updated Nov 29, 2024
Rust

lxp32-cpu

lxp32 / lxp32-cpu

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

cpu fpga assembly vhdl assembler risc wishbone soft-core risc-processor wishbone-bus risc-cpu

Updated Nov 21, 2024
Assembly

edson-acordi / 4bit-microcomputer

MikroLeo project files (schematic, PCB, assembler, emulator/debugger, circuit simulation file, documentation, example of programs etc). MikroLeo is a 4-bit microcomputer developed mainly for educational purposes and distributed for free under open-source licenses.

open-source education didactic programming cpu asm assembler computer assembly-language logic-gates alu risc oshw digital-electronics nibble 4-bit microcomputer harvard-architecture 74hctxxx

Updated Feb 29, 2024
Python

openid / sharedsignals

OpenID Shared Signals Working Group Repository

risc ssf caep sharedsignals

Updated Nov 26, 2024
Makefile

oberon

fzipp / oberon

Project Oberon RISC emulator in Go

go emulator golang oberon risc oberon-system oberon-07 wirth wirth-oberon project-oberon

Updated Nov 15, 2024
Go

ben-marshall / croyde-riscv

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

cryptography microcontroller cpu crypto verilog mit-license systemverilog risc formal-verification yosys risc-v verilator micro-controller riscv64

Updated Jan 31, 2022
SystemVerilog

SuperJMN / Plotty

C language compiler from scratch for a custom architecture, with virtual machine and all

c emulator parser csharp parsing compiler uwp virtual-machine net risc c-language superpower

Updated Jun 4, 2022
C#

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