fix(VLSU): fix segment difftest arbiter logic (#3463)

OpenXiangShan · Sep 2, 2024 · 2e0c78b · 2e0c78b
1 parent 885ce8e
commit 2e0c78b
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Showing 2 changed files with 4 additions and 3 deletions.
diff --git a/src/main/scala/xiangshan/backend/MemBlock.scala b/src/main/scala/xiangshan/backend/MemBlock.scala
@@ -1417,8 +1417,9 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
   if (env.EnableDifftest) {
     sbuffer.io.vecDifftestInfo .zipWithIndex.map{ case (sbufferPort, index) =>
       if (index == 0) {
-        sbufferPort.valid := Mux(vSegmentFlag, vSegmentUnit.io.vecDifftestInfo.valid, lsq.io.sbufferVecDifftestInfo(0).valid)
-        sbufferPort.bits  := Mux(vSegmentFlag, vSegmentUnit.io.vecDifftestInfo.bits, lsq.io.sbufferVecDifftestInfo(0).bits)
+        val vSegmentDifftestValid = vSegmentFlag && vSegmentUnit.io.vecDifftestInfo.valid
+        sbufferPort.valid := Mux(vSegmentDifftestValid, vSegmentUnit.io.vecDifftestInfo.valid, lsq.io.sbufferVecDifftestInfo(0).valid)
+        sbufferPort.bits  := Mux(vSegmentDifftestValid, vSegmentUnit.io.vecDifftestInfo.bits, lsq.io.sbufferVecDifftestInfo(0).bits)
 
         vSegmentUnit.io.vecDifftestInfo.ready  := sbufferPort.ready
         lsq.io.sbufferVecDifftestInfo(0).ready := sbufferPort.ready

diff --git a/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala b/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
@@ -521,7 +521,7 @@ class VSegmentUnit (implicit p: Parameters) extends VLSUModule
     Option(s"VSegmentUnitPipelineConnect")
   )
 
-  io.vecDifftestInfo.valid         := state === s_send_data && segmentActive
+  io.vecDifftestInfo.valid         := io.sbuffer.valid
   io.vecDifftestInfo.bits          := uopq(deqPtr.value).uop
 
   /**