timing(zacas): move isDropAmocasSta logic gen from Scheduler to NewDi…

…spatch

src/main/scala/xiangshan/backend/Bundles.scala

@@ -202,6 +202,7 @@ object Bundles {
     val vlsInstr        = Bool()
     val wfflags         = Bool()
     val isMove          = Bool()
+    val isDropAmocasSta = Bool()
     val uopIdx          = UopIdx()
     val isVset          = Bool()
     val firstUop        = Bool()

src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala

@@ -391,6 +391,10 @@ class NewDispatch(implicit p: Parameters) extends XSModule with HasPerfEvents wi
     fromRenameUpdate(i).valid := fromRename(i).valid && allowDispatch(i) && !uopBlockByIQ(i) && thisCanActualOut(i) && lsqCanAccept && !fromRename(i).bits.eliminatedMove
     fromRename(i).ready := allowDispatch(i) && !uopBlockByIQ(i) && thisCanActualOut(i) && lsqCanAccept
   }
+  for (i <- 0 until RenameWidth){
+    // check is drop amocas sta
+    fromRenameUpdate(i).bits.isDropAmocasSta := fromRename(i).bits.isAMOCAS && fromRename(i).bits.uopIdx(0) === 1.U
+  }
   var temp = 0
   allIssueParams.zipWithIndex.map{ case(issue, iqidx) => {
     for (i <- 0 until issue.numEnq){

src/main/scala/xiangshan/backend/issue/Scheduler.scala

@@ -385,6 +385,10 @@ class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBloc
   staIdx.zipWithIndex.map{ case (sta, i) => {
     io.fromDispatch.uops(sta).ready := staReady(i) && stdReady(i)
   }}
+  issueQueues.filter(iq => iq.params.StaCnt > 0).zip(staIdx).zipWithIndex.map{ case ((iq, idx),i) =>
+    iq.io.enq(i).valid := io.fromDispatch.uops(idx).valid && !io.fromDispatch.uops(idx).bits.isDropAmocasSta
+  }
+  val staValidFromDispatch = staIdx.map(idx => io.fromDispatch.uops(idx).valid)
   val memAddrIQs = issueQueues.filter(_.params.isMemAddrIQ)
   val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs
   val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0)
@@ -493,7 +497,7 @@ class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBloc
   }
 
   (stdEnqs ++ hydEnqs).zip(staEnqs ++ hyaEnqs).zipWithIndex.foreach { case ((stdIQEnq, staIQEnq), i) =>
-    stdIQEnq.valid := staIQEnq.valid && FuType.FuTypeOrR(staIQEnq.bits.fuType, FuType.stu, FuType.mou)
+    stdIQEnq.valid := staValidFromDispatch(i)
     stdIQEnq.bits  := staIQEnq.bits
     // Store data reuses store addr src(1) in dispatch2iq
     // [dispatch2iq] --src*------src*(0)--> [staIQ|hyaIQ]

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -197,6 +197,7 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
     uop.useRegCache   := DontCare
     uop.regCacheIdx   := DontCare
     uop.traceBlockInPipe := DontCare
+    uop.isDropAmocasSta := DontCare
   })
   private val inst         = Wire(Vec(RenameWidth, new XSInstBitFields))
   private val isCsr        = Wire(Vec(RenameWidth, Bool()))