area(trace, pcMem): Trace only get startAddr from pcmem

src/main/scala/xiangshan/backend/Backend.scala

@@ -1039,8 +1039,7 @@ class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle
 
   val toTop = new BackendToTopBundle
 
-  val traceCoreInterface = new TraceCoreInterface
-
+  val traceCoreInterface = new TraceCoreInterface(hasOffset = true)
   val fenceio = new FenceIO
   // Todo: merge these bundles into BackendFrontendIO
   val frontend = Flipped(new FrontendToCtrlIO)

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -278,12 +278,12 @@ class CtrlBlockImp(
   trace.io.in.fromEncoder.enable := io.traceCoreInterface.fromEncoder.enable
   trace.io.in.fromRob            := rob.io.trace.traceCommitInfo
   rob.io.trace.blockCommit       := trace.io.out.blockRobCommit
-
+  val tracePcStart = Wire(Vec(TraceGroupNum, UInt(IaddrWidth.W)))
   for ((pcMemIdx, i) <- pcMemRdIndexes("trace").zipWithIndex) {
     val traceValid = trace.toPcMem.blocks(i).valid
     pcMem.io.ren.get(pcMemIdx) := traceValid
     pcMem.io.raddr(pcMemIdx) := trace.toPcMem.blocks(i).bits.ftqIdx.get.value
-    trace.io.in.fromPcMem(i) := pcMem.io.rdata(pcMemIdx).getPc(RegEnable(trace.toPcMem.blocks(i).bits.ftqOffset.get, traceValid))
+    tracePcStart(i) := pcMem.io.rdata(pcMemIdx).startAddr
   }
 
   // Trap/Xret only occur in block(0).
@@ -296,7 +296,8 @@ class CtrlBlockImp(
   io.traceCoreInterface.toEncoder.priv       := tracePriv
   (0 until TraceGroupNum).foreach(i => {
     io.traceCoreInterface.toEncoder.groups(i).valid := trace.io.out.toEncoder.blocks(i).valid
-    io.traceCoreInterface.toEncoder.groups(i).bits.iaddr := trace.io.out.toEncoder.blocks(i).bits.iaddr.getOrElse(0.U)
+    io.traceCoreInterface.toEncoder.groups(i).bits.iaddr := tracePcStart(i)
+    io.traceCoreInterface.toEncoder.groups(i).bits.ftqOffset.foreach(_ := trace.io.out.toEncoder.blocks(i).bits.ftqOffset.getOrElse(0.U))
     io.traceCoreInterface.toEncoder.groups(i).bits.itype := trace.io.out.toEncoder.blocks(i).bits.tracePipe.itype
     io.traceCoreInterface.toEncoder.groups(i).bits.iretire := trace.io.out.toEncoder.blocks(i).bits.tracePipe.iretire
     io.traceCoreInterface.toEncoder.groups(i).bits.ilastsize := trace.io.out.toEncoder.blocks(i).bits.tracePipe.ilastsize
@@ -878,7 +879,7 @@ class CtrlBlockIO()(implicit p: Parameters, params: BackendParams) extends XSBun
     val ratOldPest = new RatToVecExcpMod
   })
 
-  val traceCoreInterface = new TraceCoreInterface
+  val traceCoreInterface = new TraceCoreInterface(hasOffset = true)
 
   val perfInfo = Output(new Bundle{
     val ctrlInfo = new Bundle {

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -328,7 +328,7 @@ class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer)
       val toL2Top      = Output(Bool())
     }
     val traceCoreInterfaceBypass = new Bundle{
-      val fromBackend = Flipped(new TraceCoreInterface)
+      val fromBackend = Flipped(new TraceCoreInterface(hasOffset = true))
       val toL2Top     = new TraceCoreInterface
     }
   })
@@ -1933,7 +1933,7 @@ class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer)
     traceFromBackend.toEncoder.priv,
     traceFromBackend.toEncoder.groups(0).valid
   )
-  (0 until TraceGroupNum).foreach{ i =>
+  (0 until TraceGroupNum).foreach { i =>
     traceToL2Top.toEncoder.groups(i).valid := RegNext(traceFromBackend.toEncoder.groups(i).valid)
     traceToL2Top.toEncoder.groups(i).bits.iretire := RegNext(traceFromBackend.toEncoder.groups(i).bits.iretire)
     traceToL2Top.toEncoder.groups(i).bits.itype := RegNext(traceFromBackend.toEncoder.groups(i).bits.itype)
@@ -1944,7 +1944,10 @@ class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer)
     traceToL2Top.toEncoder.groups(i).bits.iaddr := RegEnable(
       traceFromBackend.toEncoder.groups(i).bits.iaddr,
       traceFromBackend.toEncoder.groups(i).valid
-    )
+    ) + (RegEnable(
+      traceFromBackend.toEncoder.groups(i).bits.ftqOffset.getOrElse(0.U),
+      traceFromBackend.toEncoder.groups(i).valid
+    ) << instOffsetBits)
   }
 
 

src/main/scala/xiangshan/backend/trace/Interface.scala

@@ -36,7 +36,7 @@ class FromEncoder extends Bundle {
   val stall  = Bool()
 }
 
-class TraceCoreInterface(implicit val p: Parameters) extends Bundle with HasXSParameter {
+class TraceCoreInterface(hasOffset: Boolean = false)(implicit val p: Parameters) extends Bundle with HasXSParameter {
   val fromEncoder = Input(new Bundle {
     val enable = Bool()
     val stall  = Bool()
@@ -49,6 +49,7 @@ class TraceCoreInterface(implicit val p: Parameters) extends Bundle with HasXSPa
     }
     val groups = Vec(TraceGroupNum, ValidIO(new Bundle{
       val iaddr     = UInt(IaddrWidth.W)
+      val ftqOffset = if (hasOffset)  Some(UInt(log2Up(PredictWidth).W)) else None
       val itype     = UInt(ItypeWidth.W)
       val iretire   = UInt(IretireWidthCompressed.W)
       val ilastsize = UInt(IlastsizeWidth.W)

src/main/scala/xiangshan/backend/trace/Trace.scala

@@ -17,18 +17,17 @@ class TraceIO(implicit val p: Parameters) extends Bundle with HasXSParameter {
   val in = new Bundle {
     val fromEncoder    = Input(new FromEncoder)
     val fromRob        = Flipped(new TraceBundle(hasIaddr = false, CommitWidth, IretireWidthInPipe))
-    val fromPcMem      = Input(Vec(TraceGroupNum, UInt(IaddrWidth.W)))
   }
   val out = new Bundle {
     val toPcMem        = new TraceBundle(hasIaddr = false, TraceGroupNum, IretireWidthCompressed)
-    val toEncoder      = new TraceBundle(hasIaddr = true,  TraceGroupNum, IretireWidthCompressed)
+    val toEncoder      = new TraceBundle(hasIaddr = false,  TraceGroupNum, IretireWidthCompressed)
     val blockRobCommit = Output(Bool())
   }
 }
 
 class Trace(implicit val p: Parameters) extends Module with HasXSParameter {
   val io = IO(new TraceIO)
-  val (fromEncoder, fromRob, fromPcMem, toPcMem, toEncoder) = (io.in.fromEncoder, io.in.fromRob, io.in.fromPcMem, io.out.toPcMem, io.out.toEncoder)
+  val (fromEncoder, fromRob, toPcMem, toEncoder) = (io.in.fromEncoder, io.in.fromRob, io.out.toPcMem, io.out.toEncoder)
 
   /**
    * stage 0: CommitInfo from rob
@@ -62,13 +61,5 @@ class Trace(implicit val p: Parameters) extends Module with HasXSParameter {
   val s3_in_groups = s2_out_groups
   val s3_out_groups = RegNext(s3_in_groups)
   toPcMem := s3_in_groups
-
-  for(i <- 0 until TraceGroupNum) {
-    toEncoder.blocks(i).valid := s3_out_groups.blocks(i).valid
-    toEncoder.blocks(i).bits.iaddr.foreach(_ := Mux(s3_out_groups.blocks(i).valid, fromPcMem(i), 0.U))
-    toEncoder.blocks(i).bits.tracePipe := s3_out_groups.blocks(i).bits.tracePipe
-  }
-  if(backendParams.debugEn) {
-    dontTouch(io.out.toEncoder)
-  }
+  io.out.toEncoder := s3_out_groups
 }