fix(rv64v): not modify fflags when vl is zero (#3658)

OpenXiangShan · Sep 27, 2024 · 97e37a2 · 97e37a2
1 parent d275ad0
commit 97e37a2
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala b/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
@@ -413,7 +413,6 @@ class VFAlu(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg)
   val outFFlags = allFFlagsEn.zip(allFFlags).map{
     case(en,fflags) => Mux(en, fflags, 0.U(5.W))
   }.reduce(_ | _)
-  io.out.bits.res.fflags.get := outFFlags
 
 
   val cmpResultOldVd = Wire(UInt(cmpResultWidth.W))
@@ -498,6 +497,7 @@ class VFAlu(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg)
   resultFpMask := Mux(isFclass || isCmp, Fill(16, 1.U(1.W)), Fill(VLEN, 1.U(1.W)))
   // when dest is mask, the result need to be masked by mgtu
   io.out.bits.res.data := Mux(notModifyVd, outOldVd, Mux(outVecCtrl.isDstMask, mgtu.io.out.vd, mgu.io.out.vd) & resultFpMask)
+  io.out.bits.res.fflags.get := Mux(notModifyVd, 0.U(5.W), outFFlags)
   io.out.bits.ctrl.exceptionVec.get(ExceptionNO.illegalInstr) := mgu.io.out.illegal
 
 }