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timing(csr): remove 1 cycle to csr waddr, wdata
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@sinceforYy
sinceforYy committed Dec 3, 2024
1 parent 62fbb68 commit 9b39273
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Showing 3 changed files with 21 additions and 31 deletions.
37 changes: 16 additions & 21 deletions src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,6 @@ class NewCSRInput(implicit p: Parameters) extends Bundle {
val ren = Bool()
val op = UInt(2.W)
val addr = UInt(12.W)
val waddrReg = UInt(12.W)
val src = UInt(64.W)
val wdata = UInt(64.W)
val mnret = Input(Bool())
Expand Down Expand Up @@ -233,13 +232,11 @@ class NewCSR(implicit val p: Parameters) extends Module
/* Alias of input signals */
val wen = io.in.bits.wen && valid
val addr = io.in.bits.addr
val wdata = io.in.bits.wdata

val ren = io.in.bits.ren && valid
val raddr = io.in.bits.addr

val waddrReg = io.in.bits.waddrReg
val wdataReg = io.in.bits.wdata

val hasTrap = io.fromRob.trap.valid
val trapVec = io.fromRob.trap.bits.trapVec
val trapPC = io.fromRob.trap.bits.pc
Expand Down Expand Up @@ -296,7 +293,6 @@ class NewCSR(implicit val p: Parameters) extends Module
val legalDret = permitMod.io.out.hasLegalDret

private val wenLegalReg = GatedValidRegNext(wenLegal)
private val isModeVSReg = GatedValidRegNext(isModeVS)

var csrRwMap: SeqMap[Int, (CSRAddrWriteBundle[_], UInt)] =
machineLevelCSRMap ++
Expand Down Expand Up @@ -419,21 +415,20 @@ class NewCSR(implicit val p: Parameters) extends Module
pmpEntryMod.io.in.ren := ren
pmpEntryMod.io.in.wen := wenLegalReg
pmpEntryMod.io.in.addr := addr
pmpEntryMod.io.in.waddr := waddrReg
pmpEntryMod.io.in.wdata := wdataReg
pmpEntryMod.io.in.wdata := wdata

// Todo: all wen and wdata of CSRModule assigned in this for loop
for ((id, (wBundle, _)) <- csrRwMap) {
if (vsMapS.contains(id)) {
// VS access CSR by S: privState.isModeVS && addrMappedToVS === sMapVS(id).U
wBundle.wen := wenLegalReg && ((isModeVSReg && waddrReg === vsMapS(id).U) || (!isModeVSReg && waddrReg === id.U))
wBundle.wdata := wdataReg
wBundle.wen := wenLegalReg && ((isModeVS && addr === vsMapS(id).U) || (!isModeVS && addr === id.U))
wBundle.wdata := wdata
} else if (sMapVS.contains(id)) {
wBundle.wen := wenLegalReg && !isModeVSReg && waddrReg === id.U
wBundle.wdata := wdataReg
wBundle.wen := wenLegalReg && !isModeVS && addr === id.U
wBundle.wdata := wdata
} else {
wBundle.wen := wenLegalReg && waddrReg === id.U
wBundle.wdata := wdataReg
wBundle.wen := wenLegalReg && addr === id.U
wBundle.wdata := wdata
}
}

Expand Down Expand Up @@ -494,23 +489,23 @@ class NewCSR(implicit val p: Parameters) extends Module

miregiprios.foreach { mod =>
mod.w.wen := mireg.w.wen && (miselect.regOut.ALL.asUInt === mod.addr.U)
mod.w.wdata := wdataReg
mod.w.wdata := wdata
}

siregiprios.foreach { mod =>
mod.w.wen := sireg.w.wen && (siselect.regOut.ALL.asUInt === mod.addr.U)
mod.w.wdata := wdataReg
mod.w.wdata := wdata
}

mhartid.hartid := this.io.fromTop.hartId

cfgs.zipWithIndex.foreach { case (mod, i) =>
mod.w.wen := wenLegalReg && (waddrReg === (0x3A0 + i / 8 * 2).U)
mod.w.wen := wenLegalReg && (addr === (0x3A0 + i / 8 * 2).U)
mod.w.wdata := pmpEntryMod.io.out.pmpCfgWData(8*((i%8)+1)-1,8*(i%8))
}

pmpaddr.zipWithIndex.foreach{ case(mod, i) =>
mod.w.wen := wenLegalReg && (waddrReg === (0x3B0 + i).U)
mod.w.wen := wenLegalReg && (addr === (0x3B0 + i).U)
mod.w.wdata := pmpEntryMod.io.out.pmpAddrWData(i)
}

Expand Down Expand Up @@ -859,7 +854,7 @@ class NewCSR(implicit val p: Parameters) extends Module
)

// flush
val resetSatp = Cat(Seq(satp, vsatp, hgatp).map(_.addr.U === waddrReg)).orR && wenLegalReg // write to satp will cause the pipeline be flushed
val resetSatp = Cat(Seq(satp, vsatp, hgatp).map(_.addr.U === addr)).orR && wenLegalReg // write to satp will cause the pipeline be flushed

val floatStatusOnOff = mstatus.w.wen && (
mstatus.w.wdataFields.FS === ContextStatus.Off && mstatus.regOut.FS =/= ContextStatus.Off ||
Expand Down Expand Up @@ -1078,7 +1073,7 @@ class NewCSR(implicit val p: Parameters) extends Module
debugMod.io.in.tdata2Selected := tdata2.rdata
debugMod.io.in.tdata1Update := tdata1Update
debugMod.io.in.tdata2Update := tdata2Update
debugMod.io.in.tdata1Wdata := wdataReg
debugMod.io.in.tdata1Wdata := wdata
debugMod.io.in.triggerCanRaiseBpExp := triggerCanRaiseBpExp

entryDebugMode := debugMod.io.out.hasDebugTrap && !debugMode
Expand All @@ -1103,9 +1098,9 @@ class NewCSR(implicit val p: Parameters) extends Module
}
tdata1RegVec.zip(tdata2RegVec).zipWithIndex.map { case ((mod1, mod2), idx) => {
mod1.w.wen := tdata1Update && (tselect.rdata === idx.U)
mod1.w.wdata := wdataReg
mod1.w.wdata := wdata
mod2.w.wen := tdata2Update && (tselect.rdata === idx.U)
mod2.w.wdata := wdataReg
mod2.w.wdata := wdata
}}

triggerFrontendChange := debugMod.io.out.triggerFrontendChange
Expand Down
6 changes: 2 additions & 4 deletions src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,6 @@ class PMPEntryHandleModule(implicit p: Parameters) extends PMPModule {
val ren = io.in.ren
val wen = io.in.wen
val addr = io.in.addr
val waddr = io.in.waddr
val wdata = io.in.wdata

val pmpMask = RegInit(VecInit(Seq.fill(p(PMParameKey).NumPMP)(0.U(PMPAddrBits.W))))
Expand All @@ -36,7 +35,7 @@ class PMPEntryHandleModule(implicit p: Parameters) extends PMPModule {
// write pmpCfg
val cfgVec = WireInit(VecInit(Seq.fill(8)(0.U.asTypeOf(new PMPCfgBundle))))
for (i <- 0 until (p(PMParameKey).NumPMP/8+1) by 2) {
when (wen && (waddr === (0x3A0 + i).U)) {
when (wen && (addr === (0x3A0 + i).U)) {
for (j <- cfgVec.indices) {
val cfgOldTmp = pmpEntry(8*i/2+j).cfg
val cfgNewTmp = Wire(new PMPCfgBundle)
Expand Down Expand Up @@ -65,7 +64,7 @@ class PMPEntryHandleModule(implicit p: Parameters) extends PMPModule {
pmpAddrW(i) := pmpEntry(i).addr.ADDRESS.asUInt
pmpAddrR(i) := pmpEntry(i).addr.ADDRESS.asUInt
// write pmpAddr
when (wen && (waddr === (0x3B0 + i).U)) {
when (wen && (addr === (0x3B0 + i).U)) {
if (i != (p(PMParameKey).NumPMP - 1)) {
val addrNextLocked: Bool = PMPCfgLField.addrLocked(pmpEntry(i).cfg, pmpEntry(i + 1).cfg)
pmpMask(i) := Mux(!addrNextLocked, pmpEntry(i).matchMask(wdata), pmpEntry(i).mask)
Expand All @@ -92,7 +91,6 @@ class PMPEntryHandleIOBundle(implicit p: Parameters) extends PMPBundle {
val wen = Bool()
val ren = Bool()
val addr = UInt(12.W)
val waddr = UInt(12.W)
val wdata = UInt(64.W)
val pmpCfg = Vec(NumPMP, new PMPCfgBundle)
val pmpAddr = Vec(NumPMP, new PMPAddrBundle)
Expand Down
9 changes: 3 additions & 6 deletions src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -89,8 +89,6 @@ class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
CSROpType.isCSRRSorRC(func)
)

private val waddrReg = RegEnable(addr, 0.U(12.W), io.in.fire)
private val wdataReg = RegEnable(wdata, 0.U(64.W), io.in.fire)

csrMod.io.in match {
case in =>
Expand All @@ -99,9 +97,8 @@ class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
in.bits.ren := csrRen
in.bits.op := CSROpType.getCSROp(func)
in.bits.addr := addr
in.bits.waddrReg := waddrReg
in.bits.src := src
in.bits.wdata := wdataReg
in.bits.wdata := wdata
in.bits.mret := isMret
in.bits.mnret := isMNret
in.bits.sret := isSret
Expand Down Expand Up @@ -349,8 +346,8 @@ class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
// distribute csr write signal
// write to frontend and memory
custom.distribute_csr.w.valid := csrMod.io.distributedWenLegal
custom.distribute_csr.w.bits.addr := waddrReg
custom.distribute_csr.w.bits.data := wdataReg
custom.distribute_csr.w.bits.addr := addr
custom.distribute_csr.w.bits.data := wdata
// rename single step
custom.singlestep := csrMod.io.status.singleStepFlag
// trigger
Expand Down

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