Config: set minimal hartid width to 6

This can help users who only build one core but then manually instantiate more than two cores in the SoC.
OpenXiangShan · May 10, 2024 · f4b08c2 · f4b08c2
1 parent c686adc
commit f4b08c2
Show file tree

Hide file tree

Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/src/main/scala/top/ArgParser.scala b/src/main/scala/top/ArgParser.scala
@@ -73,7 +73,7 @@ object ArgParser {
             }
             case MaxHartIdBits =>
               require(log2Up(value.toInt) <= 10, "MaxHartIdBits should not be larger than 10.")
-              log2Up(value.toInt)
+              log2Up(value.toInt) max 6
           }), tail)
         case "--with-dramsim3" :: tail =>
           nextOption(config.alter((site, here, up) => {

diff --git a/src/main/scala/top/Configs.scala b/src/main/scala/top/Configs.scala
@@ -50,7 +50,7 @@ class BaseConfig(n: Int) extends Config((site, here, up) => {
   case ExportDebug => DebugAttachParams(protocols = Set(JTAG))
   case DebugModuleKey => Some(XSDebugModuleParams(site(XLen)))
   case JtagDTMKey => JtagDTMKey
-  case MaxHartIdBits => log2Up(n)
+  case MaxHartIdBits => log2Up(n) max 6
   case EnableJtag => true.B
 })