style(Backend): modification about FuType object, other style changes

src/main/scala/xiangshan/Parameters.scala

@@ -561,7 +561,7 @@ trait HasXSParameter {
 
   implicit val p: Parameters
 
-  def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits
+  def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Physical Memory addr bits
   final val PageOffsetWidth = 12
   def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC
 

src/main/scala/xiangshan/backend/Backend.scala

@@ -63,6 +63,9 @@ class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyMod
 
   println(params.iqWakeUpParams)
 
+  /**
+   *
+   */
   for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) {
     schdCfg.bindBackendParam(params)
   }
@@ -152,17 +155,17 @@ class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyMod
   params.updateCopyPdestInfo
   println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}")
   params.allExuParams.map(_.copyNum)
-  val ctrlBlock = LazyModule(new CtrlBlock(params))
-  val pcTargetMem = LazyModule(new PcTargetMem(params))
-  val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x)))
-  val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x)))
-  val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x)))
-  val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x)))
-  val dataPath = LazyModule(new DataPath(params))
-  val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x)))
-  val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x)))
-  val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x)))
-  val wbFuBusyTable = LazyModule(new WbFuBusyTable(params))
+  val ctrlBlock    : CtrlBlock         = LazyModule(new CtrlBlock(params))
+  val pcTargetMem  : PcTargetMem       = LazyModule(new PcTargetMem(params))
+  val intScheduler : Option[Scheduler] = params.intSchdParams.map(x => LazyModule(new Scheduler(x)))
+  val fpScheduler  : Option[Scheduler] = params.fpSchdParams.map(x => LazyModule(new Scheduler(x)))
+  val vfScheduler  : Option[Scheduler] = params.vfSchdParams.map(x => LazyModule(new Scheduler(x)))
+  val memScheduler : Option[Scheduler] = params.memSchdParams.map(x => LazyModule(new Scheduler(x)))
+  val dataPath     : DataPath          = LazyModule(new DataPath(params))
+  val intExuBlock  : Option[ExuBlock]  = params.intSchdParams.map(x => LazyModule(new ExuBlock(x)))
+  val fpExuBlock   : Option[ExuBlock]  = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x)))
+  val vfExuBlock   : Option[ExuBlock]  = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x)))
+  val wbFuBusyTable: WbFuBusyTable     = LazyModule(new WbFuBusyTable(params))
 
   lazy val module = new BackendImp(this)
 }

src/main/scala/xiangshan/backend/Bundles.scala

@@ -128,7 +128,7 @@ object Bundles {
     }
 
     def isSoftPrefetch: Bool = {
-      fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U
+      FuType.isAlu(fuType) && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U
     }
 
     def connectStaticInst(source: StaticInst): Unit = {
@@ -243,17 +243,19 @@ object Bundles {
 
     def getDebugFuType: UInt = debug_fuType.getOrElse(fuType)
 
-    def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32)
+    def isLUI: Bool = FuType.isAlu(fuType) && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32)
     def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32
-    def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi
+    def isWFI: Bool = FuType.isCsr(fuType) && fuOpType === CSROpType.wfi
 
     def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush
-    def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush
+    def isSvinval(flush: Bool) = FuType.isFence(fuType) && Cat(
+      Seq(FenceOpType.sfence, FenceOpType.hfence_v, FenceOpType.hfence_g).map(_ === fuOpType)
+    ).orR && !flush
     def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush
     def isNotSvinval = !FuType.isFence(fuType)
 
     def isHls: Bool = {
-      fuType === FuType.ldu.U && LSUOpType.isHlv(fuOpType) || fuType === FuType.stu.U && LSUOpType.isHsv(fuOpType)
+      FuType.isLoad(fuType) && LSUOpType.isHlv(fuOpType) || FuType.isStore(fuType) && LSUOpType.isHsv(fuOpType)
     }
 
     def srcIsReady: Vec[Bool] = {

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -1438,7 +1438,7 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
   val vlsuCanAccept = (0 until VlduCnt).map(
     i => vsSplit(i).io.in.ready && vlSplit(i).io.in.ready
   )
-  val isSegment     = io.ooo_to_mem.issueVldu.head.valid && isVsegls(io.ooo_to_mem.issueVldu.head.bits.uop.fuType)
+  val isSegment     = io.ooo_to_mem.issueVldu.head.valid && isVSegls(io.ooo_to_mem.issueVldu.head.bits.uop.fuType)
 
   // init port
   /**
@@ -1578,28 +1578,28 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
   val state = RegInit(s_normal)
 
   val st_atomics = Seq.tabulate(StaCnt)(i =>
-    io.ooo_to_mem.issueSta(i).valid && FuType.storeIsAMO((io.ooo_to_mem.issueSta(i).bits.uop.fuType))
+    io.ooo_to_mem.issueSta(i).valid && FuType.isAMO((io.ooo_to_mem.issueSta(i).bits.uop.fuType))
   ) ++ Seq.tabulate(HyuCnt)(i =>
-    io.ooo_to_mem.issueHya(i).valid && FuType.storeIsAMO((io.ooo_to_mem.issueHya(i).bits.uop.fuType))
+    io.ooo_to_mem.issueHya(i).valid && FuType.isAMO((io.ooo_to_mem.issueHya(i).bits.uop.fuType))
   )
 
   val st_data_atomics = Seq.tabulate(StdCnt)(i =>
-    stData(i).valid && FuType.storeIsAMO(stData(i).bits.uop.fuType)
+    stData(i).valid && FuType.isAMO(stData(i).bits.uop.fuType)
   )
 
   for (i <- 0 until StaCnt) when(st_atomics(i)) {
     io.ooo_to_mem.issueSta(i).ready := atomicsUnit.io.in.ready
     storeUnits(i).io.stin.valid := false.B
 
     state := s_atomics(i)
-    assert(!st_atomics.zipWithIndex.filterNot(_._2 == i).unzip._1.reduce(_ || _))
+    assert(!st_atomics.zipWithIndex.filterNot(_._2 == i).map(_._1).reduce(_ || _))
   }
   for (i <- 0 until HyuCnt) when(st_atomics(StaCnt + i)) {
     io.ooo_to_mem.issueHya(i).ready := atomicsUnit.io.in.ready
     hybridUnits(i).io.lsin.valid := false.B
 
     state := s_atomics(StaCnt + i)
-    assert(!st_atomics.zipWithIndex.filterNot(_._2 == StaCnt + i).unzip._1.reduce(_ || _))
+    assert(!st_atomics.zipWithIndex.filterNot(_._2 == StaCnt + i).map(_._1).reduce(_ || _))
   }
   when (atomicsUnit.io.out.valid) {
     assert((0 until StaCnt + HyuCnt).map(state === s_atomics(_)).reduce(_ || _))
@@ -1609,7 +1609,7 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
   atomicsUnit.io.in.valid := st_atomics.reduce(_ || _)
   atomicsUnit.io.in.bits  := Mux1H(Seq.tabulate(StaCnt)(i =>
     st_atomics(i) -> io.ooo_to_mem.issueSta(i).bits) ++
-    Seq.tabulate(HyuCnt)(i => st_atomics(StaCnt+i) -> io.ooo_to_mem.issueHya(i).bits))
+    Seq.tabulate(HyuCnt)(i => st_atomics(StaCnt + i) -> io.ooo_to_mem.issueHya(i).bits))
   atomicsUnit.io.storeDataIn.valid := st_data_atomics.reduce(_ || _)
   atomicsUnit.io.storeDataIn.bits  := Mux1H(Seq.tabulate(StdCnt)(i =>
     st_data_atomics(i) -> stData(i).bits))
@@ -1636,7 +1636,7 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
     atomicsUnit.io.dtlb <> amoTlb
 
     // hw prefetch should be disabled while executing atomic insts
-    loadUnits.map(i => i.io.prefetch_req.valid := false.B)
+    loadUnits.foreach(_.io.prefetch_req.valid := false.B)
 
     // make sure there's no in-flight uops in load unit
     assert(!loadUnits(0).io.ldout.valid)

src/main/scala/xiangshan/backend/decode/DecodeStage.scala

@@ -83,41 +83,63 @@ class DecodeStage(implicit p: Parameters) extends XSModule
   private val inValid = VecInit(inValids).asUInt.orR
   private val outValids = io.out.map(_.valid)
   private val outValid = VecInit(outValids).asUInt.orR
-  //readyFromRename Counter
-  val readyCounter = Mux(outReadys.head, RenameWidth.U, 0.U)
 
-  val decoderComp = Module(new DecodeUnitComp)
-  val decoders = Seq.fill(DecodeWidth)(Module(new DecodeUnit))
-  val vtypeGen = Module(new VTypeGen)
+  /** readyFromRename Counter */
+  val readyCounter: UInt = Mux(outReadys.head, RenameWidth.U, 0.U)
 
-  val debug_globalCounter = RegInit(0.U(XLEN.W))
+  /** A decoder of complex instructions */
+  private val decoderComp = Module(new DecodeUnitComp)
 
-  val canAccept = Wire(Bool())
+  /** Decoders of simple instructions, in number of DecodeWidth */
+  private val decoders = Seq.fill(DecodeWidth)(Module(new DecodeUnit))
 
-  //Simple 6
+  /** VTypeGen module, to generate vector type */
+  private val vtypeGen = Module(new VTypeGen)
+
+  private val debug_globalCounter = RegInit(0.U(XLEN.W))
+
+  val canAccept: Bool = Wire(Bool())
+
+  /**
+   * Connect inputs of simple decoders.
+   */
   decoders.zip(io.in).foreach { case (dst, src) => dst.io.enq.ctrlFlow := src.bits }
-  decoders.foreach { case dst => dst.io.csrCtrl := io.csrCtrl }
-  decoders.foreach { case dst => dst.io.fromCSR := io.fromCSR }
-  decoders.foreach { case dst => dst.io.enq.vtype := vtypeGen.io.vtype }
-  decoders.foreach { case dst => dst.io.enq.vstart := io.vstart }
-  val isComplexVec = VecInit(inValids.zip(decoders.map(_.io.deq.isComplex)).map { case (valid, isComplex) => valid && isComplex })
-  val isSimpleVec = VecInit(inValids.zip(decoders.map(_.io.deq.isComplex)).map { case (valid, isComplex) => valid && !isComplex })
-  val simpleDecodedInst = VecInit(decoders.map(_.io.deq.decodedInst))
-
-  val isIllegalInstVec = VecInit((outValids lazyZip outReadys lazyZip io.out.map(_.bits)).map {
+  decoders.foreach { _.io.csrCtrl := io.csrCtrl }
+  decoders.foreach { _.io.fromCSR := io.fromCSR }
+  decoders.foreach { _.io.enq.vtype := vtypeGen.io.vtype }
+  decoders.foreach { _.io.enq.vstart := io.vstart }
+
+  /** Whether an instruction is a complex one in input vector */
+  private val isComplexVec = VecInit(inValids.zip(decoders.map(_.io.deq.isComplex)).map {
+    case (valid, isComplex) => valid && isComplex })
+  /** Whether an instruction is a simple one in input vector */
+  private val isSimpleVec  = VecInit(inValids.zip(decoders.map(_.io.deq.isComplex)).map {
+    case (valid, isComplex) => valid && !isComplex })
+  /** Instructions decoded by simple decoders */
+  val simpleDecodedInst: Vec[DecodedInst] = VecInit(decoders.map(_.io.deq.decodedInst))
+
+  /** Whether an instruction is illegal in input vector */
+  private val isIllegalInstVec = VecInit((outValids lazyZip outReadys lazyZip io.out.map(_.bits)).map {
     case (valid, ready, decodedInst) =>
       valid && ready && (decodedInst.exceptionVec(ExceptionNO.EX_II) || decodedInst.exceptionVec(ExceptionNO.EX_VI))
   })
-  val hasIllegalInst = Cat(isIllegalInstVec).orR
-  val illegalInst = PriorityMuxDefault(isIllegalInstVec.zip(io.out.map(_.bits)), 0.U.asTypeOf(new DecodedInst))
-
-  val complexNum = Wire(UInt(3.W))
+  /** Whether the number of illegal instruction from input >= 1 */
+  private val hasIllegalInst = Cat(isIllegalInstVec).orR
+  /** Get the first illegal instruction. If all instructions are legal, get 0 */
+  val illegalInst: DecodedInst = PriorityMuxDefault(
+    isIllegalInstVec zip io.out.map(_.bits), 0.U.asTypeOf(new DecodedInst))
+
+  /** Get the first illegal instruction. If all instructions are legal, get 0 */
+  val complexNum: UInt = Wire(UInt(3.W))
   // (0, 1, 2, 3, 4, 5) + complexNum
-  val complexNumAddLocation: Vec[UInt] = VecInit((0 until DecodeWidth).map(x => (x.U +& complexNum)))
-  val noMoreThanRenameReady: Vec[Bool] = VecInit(complexNumAddLocation.map(x => x <= readyCounter))
-  val complexValid = VecInit((isComplexVec zip noMoreThanRenameReady).map(x => x._1 & x._2)).asUInt.orR
-  val complexInst = PriorityMuxDefault(isComplexVec.zip(decoders.map(_.io.deq.decodedInst)), 0.U.asTypeOf(new DecodedInst))
-  val complexUopInfo = PriorityMuxDefault(isComplexVec.zip(decoders.map(_.io.deq.uopInfo)), 0.U.asTypeOf(new UopInfo))
+  private val complexNumAddLocation: Vec[UInt] = VecInit((0 until DecodeWidth).map(_.U +& complexNum))
+  private val noMoreThanRenameReady: Vec[Bool] = VecInit(complexNumAddLocation.map(_ <= readyCounter))
+  private val complexValid = VecInit((isComplexVec zip noMoreThanRenameReady).map{
+    case (comp, noMore) => comp & noMore }).asUInt.orR
+  private val complexInst = PriorityMuxDefault(
+    isComplexVec.zip(decoders.map(_.io.deq.decodedInst)), 0.U.asTypeOf(new DecodedInst))
+  private val complexUopInfo = PriorityMuxDefault(
+    isComplexVec.zip(decoders.map(_.io.deq.uopInfo)), 0.U.asTypeOf(new UopInfo))
 
   vtypeGen.io.insts.zipWithIndex.foreach { case (inst, i) =>
     inst.valid := io.in(i).valid
@@ -151,8 +173,9 @@ class DecodeStage(implicit p: Parameters) extends XSModule
   val firstComplexOH: Vec[Bool] = VecInit(PriorityEncoderOH(isComplexVec))
 
   // block vector inst when vtype is resuming
-  val hasVectorInst = VecInit(decoders.map(x => FuType.FuTypeOrR(x.io.deq.decodedInst.fuType, FuType.vecArithOrMem ++ FuType.vecVSET))).asUInt.orR
+  val hasVectorInst = VecInit(decoders.map(x => FuType.isVAll(x.io.deq.decodedInst.fuType))).asUInt.orR
 
+  /** No redirection, no resume of VType, >=1 ready output of decodeState or complex decoder input's ready */
   canAccept := !io.redirect && (io.out.head.ready || decoderComp.io.in.ready) && !io.isResumeVType
 
   io.canAccept := canAccept