power(MemBlock): power optimization in MemBlock

src/main/scala/xiangshan/Parameters.scala

@@ -165,13 +165,13 @@ case class XSCoreParameters
   Vl_IDX: Int = 0,
   NRPhyRegs: Int = 192,
   VirtualLoadQueueSize: Int = 72,
-  LoadQueueRARSize: Int = 72,
-  LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2.
+  LoadQueueRARSize: Int = 64,
+  LoadQueueRAWSize: Int = 32, // NOTE: make sure that LoadQueueRAWSize is power of 2.
   RollbackGroupSize: Int = 8,
   LoadQueueReplaySize: Int = 72,
-  LoadUncacheBufferSize: Int = 20,
+  LoadUncacheBufferSize: Int = 4,
   LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks
-  StoreQueueSize: Int = 64,
+  StoreQueueSize: Int = 56,
   StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks
   StoreQueueForwardWithMask: Boolean = true,
   VlsQueueSize: Int = 8,

src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala

@@ -184,7 +184,8 @@ class DataSRAMBank(index: Int)(implicit p: Parameters) extends DCacheModule {
       way = 1,
       shouldReset = false,
       holdRead = false,
-      singlePort = true
+      singlePort = true,
+      withClockGate = true
     ))
   }
 
@@ -198,7 +199,6 @@ class DataSRAMBank(index: Int)(implicit p: Parameters) extends DCacheModule {
     )
     data_bank(w).io.r.req.valid := io.r.en
     data_bank(w).io.r.req.bits.apply(setIdx = io.r.addr)
-    data_bank(w).clock := ClockGate(false.B, io.r.en | (io.w.en & io.w.way_en(w)), clock)
   }
   XSPerfAccumulate("part_data_read_counter", PopCount(Cat(data_bank.map(_.io.r.req.valid))))
 

src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala

@@ -70,7 +70,7 @@ class TagArray(implicit p: Parameters) extends AbstractTagArray {
   }
 
   val tag_array = Module(new SRAMTemplate(UInt(encTagBits.W), set = nSets, way = nWays,
-    shouldReset = false, holdRead = false, singlePort = true))
+    shouldReset = false, holdRead = false, singlePort = true, withClockGate = true))
 
   val wen = rst || io.write.valid
   io.write.ready := !rst
@@ -86,7 +86,6 @@ class TagArray(implicit p: Parameters) extends AbstractTagArray {
   io.read.ready := !wen
   tag_array.io.r.req.valid := ren
   tag_array.io.r.req.bits.apply(setIdx = io.read.bits.idx)
-  tag_array.clock := ClockGate(false.B, ren | wen, clock)
   io.resp := tag_array.io.r.resp.data
 
   XSPerfAccumulate("part_tag_read_counter", tag_array.io.r.req.valid)

src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala

@@ -592,7 +592,8 @@ class PatternHistoryTable()(implicit p: Parameters) extends XSModule with HasSMS
   val pht_ram = Module(new SRAMTemplate[PhtEntry](new PhtEntry,
     set = smsParams.pht_size / smsParams.pht_ways,
     way =smsParams.pht_ways,
-    singlePort = true
+    singlePort = true,
+    withClockGate = true
   ))
   def PHT_SETS = smsParams.pht_size / smsParams.pht_ways
   // clockgated on pht_valids
@@ -805,7 +806,6 @@ class PatternHistoryTable()(implicit p: Parameters) extends XSModule with HasSMS
   pht_ram.io.w(
     s3_ram_en, s3_ram_wdata, s3_ram_waddr, s3_way_mask
   )
-  pht_ram.clock := ClockGate(false.B, s1_valid | s3_ram_en, clock)
   when(s3_valid && s3_hit){
     assert(!Cat(s3_hit_vec).andR, "sms_pht: multi-hit!")
   }