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OpenXiangShan / XiangShan Public

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area(VirtualLoadQueue): remove useless regs#4061

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cz4e wants to merge 3 commits intomasterOpenXiangShan/XiangShan:masterfrom area-vlq-rm-regsOpenXiangShan/XiangShan:area-vlq-rm-regsCopy head branch name to clipboard

+22-53

Conversation Commits3 (3)Checks Files changed

Commits

Commits on Dec 18, 2024

area(VirtualLoadQueue): remove uesless reg
cz4e
committed
fix(VirtualLoadQueue): fix vector committed update logic
cz4e
committed
style(VirtualLoadQueue): use io.ldin.bits.isvec instead of isvec
cz4e
committed

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