Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

area(LoadQueue): remove useless regs #4062

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
+2 −20
Open

area(LoadQueue): remove useless regs #4062

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 0 additions & 2 deletions src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -216,7 +216,6 @@ class LoadQueue(implicit p: Parameters) extends XSModule
* LoadQueueRAR
*/
loadQueueRAR.io.redirect <> io.redirect
loadQueueRAR.io.vecFeedback <> io.vecFeedback
loadQueueRAR.io.release <> io.release
loadQueueRAR.io.ldWbPtr <> virtualLoadQueue.io.ldWbPtr
for (w <- 0 until LoadPipelineWidth) {
Expand All @@ -229,7 +228,6 @@ class LoadQueue(implicit p: Parameters) extends XSModule
* LoadQueueRAW
*/
loadQueueRAW.io.redirect <> io.redirect
loadQueueRAW.io.vecFeedback <> io.vecFeedback
loadQueueRAW.io.storeIn <> io.sta.storeAddrIn
loadQueueRAW.io.stAddrReadySqPtr <> io.sq.stAddrReadySqPtr
loadQueueRAW.io.stIssuePtr <> io.sq.stIssuePtr
Expand Down
10 changes: 1 addition & 9 deletions src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,6 @@ class LoadQueueRAR(implicit p: Parameters) extends XSModule
val io = IO(new Bundle() {
// control
val redirect = Flipped(Valid(new Redirect))
val vecFeedback = Vec(VecLoadPipelineWidth, Flipped(ValidIO(new FeedbackToLsqIO)))

// violation query
val query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO))
Expand Down Expand Up @@ -192,18 +191,11 @@ class LoadQueueRAR(implicit p: Parameters) extends XSModule

// when the loads that "older than" current load were writebacked,
// current load will be released.
val vecLdCanceltmp = Wire(Vec(LoadQueueRARSize, Vec(VecLoadPipelineWidth, Bool())))
val vecLdCancel = Wire(Vec(LoadQueueRARSize, Bool()))
for (i <- 0 until LoadQueueRARSize) {
val deqNotBlock = !isBefore(io.ldWbPtr, uop(i).lqIdx)
val needFlush = uop(i).robIdx.needFlush(io.redirect)
val fbk = io.vecFeedback
for (j <- 0 until VecLoadPipelineWidth) {
vecLdCanceltmp(i)(j) := allocated(i) && fbk(j).valid && fbk(j).bits.isFlush && uop(i).robIdx === fbk(j).bits.robidx && uop(i).uopIdx === fbk(j).bits.uopidx
}
vecLdCancel(i) := vecLdCanceltmp(i).reduce(_ || _)

when (allocated(i) && (deqNotBlock || needFlush || vecLdCancel(i))) {
when (allocated(i) && (deqNotBlock || needFlush)) {
allocated(i) := false.B
freeMaskVec(i) := true.B
}
Expand Down
10 changes: 1 addition & 9 deletions src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,6 @@ class LoadQueueRAW(implicit p: Parameters) extends XSModule
val io = IO(new Bundle() {
// control
val redirect = Flipped(ValidIO(new Redirect))
val vecFeedback = Vec(VecLoadPipelineWidth, Flipped(ValidIO(new FeedbackToLsqIO)))

// violation query
val query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO))
Expand Down Expand Up @@ -178,18 +177,11 @@ class LoadQueueRAW(implicit p: Parameters) extends XSModule

// when the stores that "older than" current load address were ready.
// current load will be released.
val vecLdCanceltmp = Wire(Vec(LoadQueueRAWSize, Vec(VecLoadPipelineWidth, Bool())))
val vecLdCancel = Wire(Vec(LoadQueueRAWSize, Bool()))
for (i <- 0 until LoadQueueRAWSize) {
val deqNotBlock = Mux(!allAddrCheck, !isBefore(io.stAddrReadySqPtr, uop(i).sqIdx), true.B)
val needCancel = uop(i).robIdx.needFlush(io.redirect)
val fbk = io.vecFeedback
for (j <- 0 until VecLoadPipelineWidth) {
vecLdCanceltmp(i)(j) := allocated(i) && fbk(j).valid && fbk(j).bits.isFlush && uop(i).robIdx === fbk(j).bits.robidx && uop(i).uopIdx === fbk(j).bits.uopidx
}
vecLdCancel(i) := vecLdCanceltmp(i).reduce(_ || _)

when (allocated(i) && (deqNotBlock || needCancel || vecLdCancel(i))) {
when (allocated(i) && (deqNotBlock || needCancel)) {
allocated(i) := false.B
freeMaskVec(i) := true.B
}
Expand Down
Loading