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fix(scheduler): fix bug of sta valid
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xiaofeibao-xjtu committed Dec 16, 2024
1 parent 5c1a84f commit ac2e89c
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions src/main/scala/xiangshan/backend/issue/Scheduler.scala
Original file line number Diff line number Diff line change
Expand Up @@ -385,8 +385,8 @@ class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBloc
staIdx.zipWithIndex.map{ case (sta, i) => {
io.fromDispatch.uops(sta).ready := staReady(i) && stdReady(i)
}}
issueQueues.filter(iq => iq.params.StaCnt > 0).zip(staIdx).zipWithIndex.map{ case ((iq, idx),i) =>
iq.io.enq(i).valid := io.fromDispatch.uops(idx).valid && !io.fromDispatch.uops(idx).bits.isDropAmocasSta
issueQueues.filter(iq => iq.params.StaCnt > 0).map(_.io.enq).flatten.zipWithIndex.map{ case (iq, idx) =>
iq.valid := io.fromDispatch.uops(staIdx(idx)).valid && !io.fromDispatch.uops(staIdx(idx)).bits.isDropAmocasSta
}
val staValidFromDispatch = staIdx.map(idx => io.fromDispatch.uops(idx).valid)
val memAddrIQs = issueQueues.filter(_.params.isMemAddrIQ)
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