power(MemBlock): add static clock gated (tmp Branch for Test) #3716

jin120811 · 2024-10-11T09:45:23Z

No description provided.

…etermined, no need to be stored in the Queue.

…optimize

….imm(32bits), because can use vaddr directly

…ache'

XiangShanRobot · 2024-10-11T15:55:23Z

[Generated by IPC robot]
commit: c953888

commit	astar	copy_and_run	coremark	gcc	gromacs	lbm	linux	mcf	microbench	milc	namd	povray	wrf	xalancbmk
`c953888`	1.926	0.451	2.705	1.192	2.824	2.464	2.401	0.920	1.394	1.616	3.413	2.734	2.419	3.275

master branch:

commit	astar	copy_and_run	coremark	gcc	gromacs	lbm	linux	mcf	microbench	milc	namd	povray	wrf	xalancbmk
`ecac006`	1.926	0.451	2.705	1.192	2.824	2.464	2.401	0.920	1.394	1.616	3.413	2.734	2.419	3.275
`9acb8f9`	1.926	0.451	2.705	1.192	2.824	2.464	2.401	0.920	1.394	1.616	3.413	2.734	2.419	3.275
`d904dcf`	1.926	0.451	2.705	1.192	2.824	2.464	2.401	0.920	1.394	1.616	3.413	2.734	2.419	3.275
`9d3877d`	1.928	0.450	2.703	1.192	2.812	2.465	2.400	0.915	1.395	1.626	3.420	2.755	2.428	3.271
`2b20b83`	1.928	0.450	2.703	1.192	2.812	2.465	2.400	0.915	1.395	1.626	3.420	2.755	2.428	3.271
`8bb30a5`	1.928	0.450	2.703	1.192	2.812	2.465	2.400	0.915	1.395	1.626	3.420	2.755	2.428	3.271
`7a59a48`	1.935	0.450	2.703	1.192	2.812	2.465	2.400	0.915	1.395	1.626	3.420	2.755	2.428	3.271
`676ddb7`	1.936	0.450	2.701	1.198	2.812	2.465	2.403	0.914	1.394	1.626	3.424	2.745	2.428	3.271
`0861ab0`	1.936	0.450	2.701	1.198	2.812	2.465	2.403	0.914	1.394	1.626	3.424	2.745	2.428	3.271
`ea2894c`	1.924	0.450	2.701	1.198	2.812	2.465	2.403	0.914	1.394	1.626	3.424	2.745	2.428	3.271

jin120811 added 11 commits October 11, 2024 17:28

area(MemBlock): optimise 'exceptionVec' redundant bits for PPA

466f2fd

area(MemBlock): optimise 'fuType', the fuType of uop in pipeline is d…

c6384e1

…etermined, no need to be stored in the Queue.

area(VSplit): uop.imm is constant zero when uop is vector, so should …

a6a9b6a

…optimize

area(StoreUnit): source from StoreMisalignBuffer don't need store uop…

8b5efbe

….imm(32bits), because can use vaddr directly

area(LoadQueueReplay): optimise exceptionVec(loadAddrMisaligned)

194a190

power(MemBlock): add clockgate for sfence

1ece486

power(LoadPipe): add clockgate for 'io.replace_access.bits.set'

5dabc0a

power(L2TLB, TLB): add clockgated for sfence

97896fb

power(MisalignBuffer): add clockgate for s2_req use valid

948102a

power(LoadUnit): add clockgate for 's3_mmio', 's3_ld_raw_data_frm_unc…

a959afb

…ache'

fix(LDU): fix x-value in vcs

c953888

jin120811 added do not merge Do not merge this pull request power about power design or optimization labels Oct 11, 2024

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