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area(VirtualLoadQueue): remove useless regs #4061

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area(VirtualLoadQueue): remove useless regs #4061

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6346152
area(VirtualLoadQueue): remove uesless reg
cz4e Dec 18, 2024
d565f5a
fix(VirtualLoadQueue): fix vector committed update logic
cz4e Dec 18, 2024
5340cd5
style(VirtualLoadQueue): use io.ldin.bits.isvec instead of isvec
cz4e Dec 18, 2024
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75 changes: 22 additions & 53 deletions src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ import xiangshan.ExceptionNO._
import xiangshan.cache._
import utils._
import utility._
import xiangshan.backend.Bundles.{DynInst, MemExuOutput}
import xiangshan.backend.Bundles.{DynInst, MemExuOutput, UopIdx}
import xiangshan.backend.fu.FuConfig.LduCfg
import xiangshan.backend.decode.isa.bitfield.{InstVType, XSInstBitFields}
import xiangshan.backend.fu.FuType
Expand Down Expand Up @@ -63,12 +63,10 @@ class VirtualLoadQueue(implicit p: Parameters) extends XSModule
// MicroOp : inst's microOp
// Flags : load flags
val allocated = RegInit(VecInit(List.fill(VirtualLoadQueueSize)(false.B))) // The control signals need to explicitly indicate the initial value
val uop = Reg(Vec(VirtualLoadQueueSize, new DynInst))
val addrvalid = RegInit(VecInit(List.fill(VirtualLoadQueueSize)(false.B))) // non-mmio addr is valid
val datavalid = RegInit(VecInit(List.fill(VirtualLoadQueueSize)(false.B))) // non-mmio data is valid
// vector load: inst -> uop (pdest registor) -> flow (once load operation in loadunit)
val robIdx = Reg(Vec(VirtualLoadQueueSize, new RobPtr))
val uopIdx = Reg(Vec(VirtualLoadQueueSize, UopIdx()))
val isvec = RegInit(VecInit(List.fill(VirtualLoadQueueSize)(false.B))) // vector load flow
val veccommitted = RegInit(VecInit(List.fill(VirtualLoadQueueSize)(false.B))) // vector load uop has commited
val committed = Reg(Vec(VirtualLoadQueueSize, Bool()))

/**
* used for debug
Expand All @@ -92,7 +90,7 @@ class VirtualLoadQueue(implicit p: Parameters) extends XSModule
val allowEnqueue = validCount <= (VirtualLoadQueueSize - LSQLdEnqWidth).U
val canEnqueue = io.enq.req.map(_.valid)
val needCancel = WireInit(VecInit((0 until VirtualLoadQueueSize).map(i => {
uop(i).robIdx.needFlush(io.redirect) && allocated(i)
robIdx(i).needFlush(io.redirect) && allocated(i)
})))
val lastNeedCancel = GatedValidRegNext(needCancel)
val enqCancel = canEnqueue.zip(io.enq.req).map{case (v , x) =>
Expand Down Expand Up @@ -133,9 +131,7 @@ class VirtualLoadQueue(implicit p: Parameters) extends XSModule
val DeqPtrMoveStride = CommitWidth
require(DeqPtrMoveStride == CommitWidth, "DeqPtrMoveStride must be equal to CommitWidth!")
val deqLookupVec = VecInit((0 until DeqPtrMoveStride).map(deqPtr + _.U))
val deqLookup = VecInit(deqLookupVec.map(ptr => allocated(ptr.value)
&& ((datavalid(ptr.value) && addrvalid(ptr.value) && !isvec(ptr.value)) || (isvec(ptr.value) && veccommitted(ptr.value)))
&& ptr =/= enqPtrExt(0)))
val deqLookup = VecInit(deqLookupVec.map(ptr => allocated(ptr.value) && committed(ptr.value) && ptr =/= enqPtrExt(0)))
val deqInSameRedirectCycle = VecInit(deqLookupVec.map(ptr => needCancel(ptr.value)))
// make chisel happy
val deqCountMask = Wire(UInt(DeqPtrMoveStride.W))
Expand Down Expand Up @@ -170,19 +166,18 @@ class VirtualLoadQueue(implicit p: Parameters) extends XSModule
// 16 2 2 2 2 2.
// Therefore, VecMemLSQEnqIteratorNumberSeq = Seq(16, 2, 2, 2, 2, 2)
for (j <- 0 until VecMemLSQEnqIteratorNumberSeq(i)) {
val enqIdx = (index + j.U).value
when (j.U < validVLoadOffset(i)) {
allocated((index + j.U).value) := true.B
uop((index + j.U).value) := io.enq.req(i).bits
uop((index + j.U).value).lqIdx := lqIdx + j.U
allocated(enqIdx) := true.B
robIdx(enqIdx) := io.enq.req(i).bits.robIdx
uopIdx(enqIdx) := io.enq.req(i).bits.uopIdx

// init
addrvalid((index + j.U).value) := false.B
datavalid((index + j.U).value) := false.B
isvec((index + j.U).value) := FuType.isVLoad(io.enq.req(i).bits.fuType)
veccommitted((index + j.U).value) := false.B
isvec(enqIdx) := FuType.isVLoad(io.enq.req(i).bits.fuType)
committed(enqIdx) := false.B

debug_mmio((index + j.U).value) := false.B
debug_paddr((index + j.U).value) := 0.U
debug_mmio(enqIdx) := false.B
debug_paddr(enqIdx) := 0.U

XSError(!io.enq.canAccept || !io.enq.sqCanAccept, s"must accept $i\n")
XSError(index.value =/= lqIdx.value, s"must be the same entry $i\n")
Expand Down Expand Up @@ -210,12 +205,12 @@ class VirtualLoadQueue(implicit p: Parameters) extends XSModule
for (i <- 0 until VirtualLoadQueueSize) {
val cmt = io.vecCommit
for (j <- 0 until VecLoadPipelineWidth) {
vecLdCommittmp(i)(j) := allocated(i) && cmt(j).valid && uop(i).robIdx === cmt(j).bits.robidx && uop(i).uopIdx === cmt(j).bits.uopidx
vecLdCommittmp(i)(j) := allocated(i) && cmt(j).valid && robIdx(i) === cmt(j).bits.robidx && uopIdx(i) === cmt(j).bits.uopidx
}
vecLdCommit(i) := vecLdCommittmp(i).reduce(_ || _)

when (vecLdCommit(i)) {
veccommitted(i) := true.B
when (vecLdCommit(i) && isvec(i)) {
committed(i) := true.B
}
}

Expand Down Expand Up @@ -247,31 +242,8 @@ class VirtualLoadQueue(implicit p: Parameters) extends XSModule
val need_rep = io.ldin(i).bits.rep_info.need_rep
val need_valid = io.ldin(i).bits.updateAddrValid

when (!need_rep && need_valid) {
// update control flag
addrvalid(loadWbIndex) := hasExceptions || !io.ldin(i).bits.tlbMiss || io.ldin(i).bits.isSWPrefetch
datavalid(loadWbIndex) :=
(if (EnableFastForward) {
hasExceptions ||
io.ldin(i).bits.mmio ||
!io.ldin(i).bits.miss && // dcache miss
!io.ldin(i).bits.dcacheRequireReplay || // do not writeback if that inst will be resend from rs
io.ldin(i).bits.isSWPrefetch
} else {
hasExceptions ||
io.ldin(i).bits.mmio ||
!io.ldin(i).bits.miss ||
io.ldin(i).bits.isSWPrefetch
})

//
when (io.ldin(i).bits.data_wen_dup(1)) {
uop(loadWbIndex) := io.ldin(i).bits.uop
}
when (io.ldin(i).bits.data_wen_dup(4)) {
uop(loadWbIndex).debugInfo := io.ldin(i).bits.uop.debugInfo
}
uop(loadWbIndex).debugInfo := io.ldin(i).bits.rep_info.debug
when (!need_rep && need_valid && !io.ldin(i).bits.isvec) {
committed(loadWbIndex) := true.B

// Debug info
debug_mmio(loadWbIndex) := io.ldin(i).bits.mmio
Expand Down Expand Up @@ -313,12 +285,9 @@ class VirtualLoadQueue(implicit p: Parameters) extends XSModule
}

for (i <- 0 until VirtualLoadQueueSize) {
XSDebug(s"$i pc %x pa %x ", uop(i).pc, debug_paddr(i))
PrintFlag(allocated(i), "v")
PrintFlag(allocated(i) && datavalid(i), "d")
PrintFlag(allocated(i) && addrvalid(i), "a")
PrintFlag(allocated(i) && addrvalid(i) && datavalid(i), "w")
PrintFlag(allocated(i) && isvec(i), "c")
PrintFlag(allocated(i), "a")
PrintFlag(allocated(i) && committed(i), "c")
PrintFlag(allocated(i) && isvec(i), "v")
XSDebug(false, true.B, "\n")
}
// end
Expand Down
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