Skip to content

Actions: jon011235/MARVIN

Actions

All workflows

Actions

Loading...
Loading

Showing runs from all workflows
61 workflow runs
61 workflow runs

Filter by Event

Filter by Status

Filter by Branch

Filter by Actor

Create and set up Quartus project Verible linter example #8: Pull request #13 synchronize by iJustLeyxo
October 28, 2023 10:04 1m 7s quartus-project
quartus-project
October 28, 2023 10:04 1m 7s
Create and set up Quartus project Verible linter example #7: Pull request #13 opened by iJustLeyxo
October 28, 2023 01:38 1m 12s quartus-project
quartus-project
October 28, 2023 01:38 1m 12s
Repair gitignore remove comment in include statement Verible linter example #6: Pull request #12 opened by iJustLeyxo
October 27, 2023 10:40 1m 16s gitignore
gitignore
October 27, 2023 10:40 1m 16s
Repair .gitignore remove indentations use empty lines instead Verible linter example #5: Pull request #11 opened by iJustLeyxo
October 27, 2023 10:18 1m 5s gitignore
gitignore
October 27, 2023 10:18 1m 5s
Rename verilog-compiler.vhdl to verilog-compiler.yml Verible linter example #4: Pull request #9 synchronize by jon011235
October 26, 2023 09:23 1m 10s correcting-stupid-error
correcting-stupid-error
October 26, 2023 09:23 1m 10s
Rename verilog-compiler.vhdl to verilog-compiler.yml Verible linter example #3: Pull request #9 synchronize by jon011235
October 26, 2023 09:13 1m 29s correcting-stupid-error
correcting-stupid-error
October 26, 2023 09:13 1m 29s
Rename verilog-compiler.vhdl to verilog-compiler.yml Verilog Build and Analysis #3: Pull request #9 synchronize by jon011235
October 26, 2023 09:13 11m 32s correcting-stupid-error
correcting-stupid-error
October 26, 2023 09:13 11m 32s
Rename verilog-compiler.vhdl to verilog-compiler.yml Verilog Build and Analysis #2: Pull request #9 synchronize by jon011235
October 26, 2023 08:56 8m 8s correcting-stupid-error
correcting-stupid-error
October 26, 2023 08:56 8m 8s
Rename verilog-compiler.vhdl to verilog-compiler.yml Verible linter example #2: Pull request #9 synchronize by jon011235
October 26, 2023 08:56 36s correcting-stupid-error
correcting-stupid-error
October 26, 2023 08:56 36s
Rename verilog-compiler.vhdl to verilog-compiler.yml Verible linter example #1: Pull request #9 synchronize by iJustLeyxo
October 25, 2023 18:58 16s correcting-stupid-error
correcting-stupid-error
October 25, 2023 18:58 16s
Rename verilog-compiler.vhdl to verilog-compiler.yml Verilog Build and Analysis #1: Pull request #9 synchronize by iJustLeyxo
October 25, 2023 18:58 4m 50s correcting-stupid-error
correcting-stupid-error
October 25, 2023 18:58 4m 50s